From: Avi Kivity <avi@qumranet.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: Jesse Barnes <jesse.barnes@intel.com>, Howard Chu <hyc@symas.com>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: MTRR initialization
Date: Thu, 20 Sep 2007 14:05:28 +0200 [thread overview]
Message-ID: <46F26208.309@qumranet.com> (raw)
In-Reply-To: <p73d4wdal00.fsf@bingen.suse.de>
Andi Kleen wrote:
> Jesse Barnes <jesse.barnes@intel.com> writes:
>
>> To do this in a nicer way (and be less vulnerable to similar BIOS
>> funkiness) the kernel really needs full PAT support. That should allow
>> WC over WB and WC over UC mappings to occur, at least if I'm
>> remembering the docs right...
>>
>
> PAT only really helps for device driver performance optimizations.
> But if the basic WB MTRRs are wrong PAT cannot really salvage it.
>
Is there any reason not to set the MTRRs to define the entire memory as
write back, and use PAT exclusively for setting cacheability?
On my home machine for instance, the BIOS uses all 8 MTRRs leaving none
for X. I hacked it by merging a couple of MTRRs but this isn't a
generic solution.
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2007-09-20 12:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-14 16:33 MTRR initialization Howard Chu
2007-09-14 17:12 ` Yinghai Lu
2007-09-16 16:08 ` Howard Chu
2007-09-16 17:53 ` Yinghai Lu
2007-09-16 18:40 ` Eric W. Biederman
2007-09-18 17:53 ` Howard Chu
2007-09-18 18:18 ` Eric W. Biederman
2007-09-19 21:52 ` Jesse Barnes
2007-09-20 6:50 ` Andi Kleen
2007-09-20 12:05 ` Avi Kivity [this message]
2007-09-20 12:10 ` Andi Kleen
2007-09-20 12:46 ` Avi Kivity
2007-09-20 15:03 ` Jesse Barnes
2007-09-20 17:08 ` Jesse Barnes
2007-09-22 0:27 ` Siddha, Suresh B
2007-09-22 0:46 ` Howard Chu
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