Re: [rfc][patch 3/3] x86: optimise barriers

[Helge Hafting <helge.hafting@aitel.hist.no>]

Jarek Poplawski wrote:
> On 04-10-2007 07:23, Nick Piggin wrote:
>   
>> According to latest memory ordering specification documents from Intel and
>> AMD, both manufacturers are committed to in-order loads from cacheable memory
>> for the x86 architecture. Hence, smp_rmb() may be a simple barrier.
>>     
> ...
>
> Great news!
>
> First it looks like a really great thing that it's revealed at last.
> But then... there is probably some confusion: did we have to use
> ineffective code for so long?
>   
You could have tried the optimization before, and
gotten better performance. But if without solid knowledge that
the optimization is _valid_, you risk having a kernel
that performs great but suffer the occational glitch and
therefore is unstable and crash the machine "now and then".
This sort of thing can't really be figured out by experimentation, because
the bad cases might happen only with some processors, some
combinations of memory/chipsets, or with some minimum
number of processors.  Such problems can be very hard
to find, especially considering that other plain bugs also
cause crashes.

Therefore, the "ineffective code" was used because it was
the only safe alternative. Now we know, so now we may optimize.


Helge Hafting