From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
To: Dave Hansen <dave.hansen@intel.com>, kvm@vger.kernel.org
Cc: pbonzini@redhat.com, jmattson@google.com, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, x86@kernel.org,
sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, joro@8bytes.org,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, linux-kernel@vger.kernel.org,
hpa@zytor.com
Subject: Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature
Date: Fri, 11 Sep 2020 13:10:30 -0700 [thread overview]
Message-ID: <472e71a4-e50e-1d39-3088-cc103c79ddb3@oracle.com> (raw)
In-Reply-To: <c5cbc91e-f576-5cc7-a40c-c11abaea4ad2@intel.com>
On 9/11/20 12:36 PM, Dave Hansen wrote:
> On 9/11/20 12:25 PM, Krish Sadhukhan wrote:
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 81335e6fe47d..0e5b27ee5931 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -293,6 +293,7 @@
>> #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
>> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
>> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
>> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */
> That's an awfully generic name. We generally have "hardware-enforced
> cache coherency" already everywhere. :)
>
> This probably needs to say something about encryption, or even SEV
> specifically.
How about X86_FEATURE_ENC_CACHE_COHERENCY ?
> I also don't see this bit in the "AMD64 Architecture
> Programmer’s Manual". Did I look in the wrong spot somehow?
Section 7.10.6 in APM mentions this.
next prev parent reply other threads:[~2020-09-11 20:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 19:25 [PATCH 0/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-11 19:25 ` [PATCH 1/4 v3] x86: AMD: Replace numeric value for SME CPUID leaf with a #define Krish Sadhukhan
2020-09-11 21:21 ` Borislav Petkov
2020-09-12 6:54 ` Paolo Bonzini
2020-09-11 19:25 ` [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-11 19:36 ` Dave Hansen
2020-09-11 20:10 ` Krish Sadhukhan [this message]
2020-09-11 20:58 ` Dave Hansen
2020-09-11 21:33 ` Borislav Petkov
2020-09-11 21:44 ` Tom Lendacky
2020-09-11 19:26 ` [PATCH 3/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains Krish Sadhukhan
2020-09-11 19:26 ` [PATCH 4/4 v3] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
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