From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753496AbcALW2Z (ORCPT ); Tue, 12 Jan 2016 17:28:25 -0500 Received: from mout.kundenserver.de ([212.227.126.135]:58490 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750915AbcALW2X (ORCPT ); Tue, 12 Jan 2016 17:28:23 -0500 From: Arnd Bergmann To: Bharat Kumar Gogada Cc: bhelgaas@google.com, michals@xilinx.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 12 Jan 2016 23:27:25 +0100 Message-ID: <4734542.KZZp0TeeeM@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1452620173-4905-4-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:5GZOIswt099PCTK+Gk6FzBqBN8dfMWmBWcKWpCnDyhC0Kpjdagz CPQ/SY4D0UBwUGVgvLpfqbjWeR3GZ6IVFlL2mhtzIsJS+txiyqXTKbRa7McIbu8jcGJ/H+h zdsF1lGHRyI5XbycRZ17pAaKp0EsoV6FJJH2OAJLM3MfCBpbs497r3TnECd1HNyNzfJFtNO +3dNsj8sz/7ghCL3LQmMQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:W88oz1QDKjA=:FCb+dnRj4YteN+fEVVF7dn nwF3wHpLmjaosmHrHx5U9KfOiucM2Ai7j+A1Q5t3QPc1igaJE5YAgefzk/aYMe4Ai/VOgtpsI OCHwyl+UPFDzYAxAujoIApRF+LP4oXQ8KoQbuyZ91v9ESBpAn9kRO+tqLRAZI+om/wdOT0vlR U1npC0iljnaXDP5yvLFLekuIAkD/wN5ZGSi3Ys/86ZZmqNZjcJRgjovKBI7KZ/LMLksUi3TfP NT0AInJOxBzMjxWJbGSFg/Y3Y/ODkaKxCT8CImpVnitRxnNGFhaliNqZe17SA6vYgw9qxPcMw 8o8N8lPBH9UqR4rSinbDJ21CofF4ph9zTfWjakaQzK+iG0PyVjLRs+8zTX1XDOLQy18p0f9Nr 9xuja7VUyLyIS1TPiAGbydIcX7+FKnnGA8JZ069JTC1U4vR9I9EEcpDkN4TfKu+7amKab55V5 J6+qaR83iCDB6SP/U400eufW1AIyTLNm1pnB9klXuiUPgpQZPMXM4+xKgC4zC+UEsUNBhVSlR BH4dGqdrd1ET/qmqedmZJVMmJyEG85EQDTSyikwmPkhBTHaqFd6OwtoG8SyVaWgDOI5TYNMlq Pr/sB1Un1VP1EbQJ5y5f/WCnbIyJZHFRWe38UXl6tIJn73YAFB7Gw05llhpDopkD6sPjrkEMb EdrnlaPtqfaTyoBBZN+XjUbK7elGxVIpS+HWfprfUE8mnxVWxhjTM2bJc99q6AqucOHSoGTeB OrNwhbMT8Ql0pbYC Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > Zynq and Microblaze Architectures. > With these modifications drivers/pci/host/pcie-xilinx.c, will > work on both Zynq and Microblaze Architectures. > > Signed-off-by: Bharat Kumar Gogada > Signed-off-by: Ravi Kiran Gummaluri I think this patch should be split into three, as you are doing three unrelated things here. > --- > Changes: > Changed Total number of MSI IRQ count logic according to both architectures. > Updated MSI assigning functions accordingly to new count. > Modified irq_domain_add_linear with new MSI IRQ count. > Added #ifdef to pci_fixup_irqs which is ARM specific API. > --- > drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c > index 3e3757f..1981948 100644 > --- a/drivers/pci/host/pcie-xilinx.c > +++ b/drivers/pci/host/pcie-xilinx.c > @@ -92,7 +92,12 @@ > #define ECAM_DEV_NUM_SHIFT 12 > > /* Number of MSI IRQs */ > -#define XILINX_NUM_MSI_IRQS 128 > +#define XILINX_NUM_MSI_IRQS 128 > +#ifdef CONFIG_ARM > +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > +#else > +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > +#endif Something looks wrong here in the microblaze variant. What does NR_IRQS have to do with it? > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) > */ > static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) > { > + int irq; > int pos; > > pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); > - if (pos < XILINX_NUM_MSI_IRQS) > + irq = pos; > +#ifdef CONFIG_MICROBLAZE > + irq = XILINX_NUM_MSI_IRQS + pos; > +#endif if (IS_ENABLED(CONFIG_MICROBLAZE)) irq = XILINX_NUM_MSI_IRQS + pos; > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) > #endif > pci_scan_child_bus(bus); > pci_assign_unassigned_bus_resources(bus); > +#ifdef CONFIG_ARM > pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > +#endif > pci_bus_add_devices(bus); > platform_set_drvdata(pdev, port); Here it looks like microblaze gets it right. I'm not sure why we still need the pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in common code. Arnd