On 01-01-08 22:15, H. Peter Anvin wrote:

> I have mentioned this before... I think writing zero to port 0xf0 would 
> be an acceptable pause interface (to the extent where we need an I/O 
> port) except on 386 with 387 present; on those systems we can fall back 
> to 0x80.

PII 400 / Intel 440 BX (PIIX4):

rene@6bap:~/port80$ su -c ./portime
out 0x80: 544 cycles
in  0x80: 254 cycles
in  0x61: 254 cycles
out 0xf0: 544 cycles

The Intel PIIX/PIIX3 datasheet specifically mentions that both reads and 
writes at 0xf0 "flow through to the ISA bus".

However, more complete, it says:

"Writing to this register causes the PIIX/PIIX3 to assert IGNNE#. The 
PIIX/PIIX3 also negates IRQ13 (internal to the PIIX). Note that IGNNE# is 
not asserted unless FERR# is active. Reads/writes flow through to the ISA bus".

We don't want the side-effects, do we?

Rene.