From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-176.mta0.migadu.com (out-176.mta0.migadu.com [91.218.175.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 934FF1F03EA for ; Tue, 21 Jan 2025 13:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737466967; cv=none; b=dU0OlVcE/QAJ5t2CZKNOvFhYSMXLa5rFQcug5vVvPT6aVI1LKghgnnD7IrzAeCEr0OU4Hrz/JjNLRSsHxtQSGvx4cHEsXFi6A+nkr2prlIPHGg0FMAU4JQzt1hkD/wUpjeHAeXv+Y8ha790YVRDQPRIitNfwukjikM7sGPs+LCw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737466967; c=relaxed/simple; bh=VTAJbNnVhlrhpHc7hXfvvLJEz/sYd1BNf5Sd/b1wzTU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=WZ0Hcj/C3m1LIaZVAdtGYQDuEKt/9/bEz3x7h37xbYoRWvyNtVEdgQXBoaaVagMecHQ/TwDqeNeKhm9Y/YnTky0MRjWjghv6cy60+WK0hp/ww/RE3Fu/1WD7mhHuvWBcFmk0u3lnQZiNAmSkJ1NnwHPm2kmGz37npswZZOhTsyA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=htEFROgp; arc=none smtp.client-ip=91.218.175.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="htEFROgp" Message-ID: <4787f868-a384-4753-8cfd-3027f5c88fd0@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737466957; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=riUwlOLV98LIWuaBGw9AYLP5twrEkbqsTzI6ivE/+oM=; b=htEFROgpRDTuwyLUcbA8L+AEPC0TWS6DsHAhCftehljl3B20RKP+a50aboJaspD7NlDJ1A D5sFvKnEdYpeljOCvdf85vkeRWbc6/BituX4itOFrXC6V6kr1GMao2bb6d0GO5292Xh003 dRZAt5RY1NT0+3Tqo59h3hNQbBPSF1Q= Date: Tue, 21 Jan 2025 21:41:46 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH] net: stmmac: dwmac-loongson: Add fix_soc_reset function To: Qunqin Zhao , kuba@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com Cc: chenhuacai@kernel.org, fancer.lancer@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250121082536.11752-1-zhaoqunqin@loongson.cn> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Yanteng Si In-Reply-To: <20250121082536.11752-1-zhaoqunqin@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT 在 1/21/25 16:25, Qunqin Zhao 写道: > Loongson's GMAC device takes nearly two seconds to complete DMA reset, > however, the default waiting time for reset is 200 milliseconds Is only GMAC like this? > > Signed-off-by: Qunqin Zhao > --- > .../net/ethernet/stmicro/stmmac/dwmac-loongson.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > index bfe6e2d631bd..35639d26256c 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > @@ -516,6 +516,18 @@ static int loongson_dwmac_acpi_config(struct pci_dev *pdev, > return 0; > } > How about putting a part of the commit message here as a comment? > +static int loongson_fix_soc_reset(void *priv, void __iomem *ioaddr) > +{ > + u32 value = readl(ioaddr + DMA_BUS_MODE); > + > + value |= DMA_BUS_MODE_SFT_RESET; > + writel(value, ioaddr + DMA_BUS_MODE); > + > + return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, > + !(value & DMA_BUS_MODE_SFT_RESET), > + 10000, 2000000); > +} > + > static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > struct plat_stmmacenet_data *plat; > @@ -566,6 +578,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id > > plat->bsp_priv = ld; > plat->setup = loongson_dwmac_setup; > + plat->fix_soc_reset = loongson_fix_soc_reset; If only GMAC needs to be done this way, how about putting it inside the loongson_gmac_data()? Thanks, Yanteng