[PATCH] [7/8] CPA: Don't flush caches on CPUs that support self-snoop

Andi Kleen
2008-02-11T09:52:31Z

[2.6.25 candidate I believe]

The specification of SS in the public manuals is a little unclear,
but I got confirmation from Intel that SS implies that there is no cache
flush needed on caching attribute changes.

Signed-off-by: Andi Kleen <ak@suse.de>

---
arch/x86/mm/pageattr.c | 5 ++++-
include/asm-x86/cpufeature.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)

Index: linux/arch/x86/mm/pageattr.c
===================================================================
--- linux.orig/arch/x86/mm/pageattr.c
+++ linux/arch/x86/mm/pageattr.c
@@ -74,7 +74,7 @@ static void __cpa_flush_all(void *arg)
*/
__flush_tlb_all();

- if (cache && boot_cpu_data.x86_model >= 4)
+ if (!cpu_has_ss && cache && boot_cpu_data.x86_model >= 4)
wbinvd();
}

@@ -108,6 +108,9 @@ static void cpa_flush_range(unsigned lon
if (!cache)
return;

+ if (cpu_has_ss)
+ return;
+
/*
* We only need to flush on one CPU,
* clflush is a MESI-coherent instruction that
Index: linux/include/asm-x86/cpufeature.h
===================================================================
--- linux.orig/include/asm-x86/cpufeature.h
+++ linux/include/asm-x86/cpufeature.h
@@ -157,6 +157,7 @@ extern const char * const x86_power_flag
#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
+#define cpu_has_ss boot_cpu_has(X86_FEATURE_SELFSNOOP)
#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)