From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762272AbYD0WcU (ORCPT ); Sun, 27 Apr 2008 18:32:20 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752108AbYD0WcJ (ORCPT ); Sun, 27 Apr 2008 18:32:09 -0400 Received: from terminus.zytor.com ([198.137.202.10]:57523 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750885AbYD0WcI (ORCPT ); Sun, 27 Apr 2008 18:32:08 -0400 Message-ID: <4814FED5.4090509@zytor.com> Date: Sun, 27 Apr 2008 15:31:49 -0700 From: "H. Peter Anvin" User-Agent: Thunderbird 2.0.0.12 (X11/20080226) MIME-Version: 1.0 To: James Bottomley CC: Ingo Molnar , Thomas Gleixner , linux-kernel Subject: Re: Breakage caused by unreviewed patch in x86 tree References: <1209329485.3801.46.camel@localhost.localdomain> <4814F76B.8030505@zytor.com> <1209334212.3801.70.camel@localhost.localdomain> <4814FAA0.8060705@zytor.com> <1209334729.3801.75.camel@localhost.localdomain> In-Reply-To: <1209334729.3801.75.camel@localhost.localdomain> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org James Bottomley wrote: >>> Yes, that's the one ... but I believe a class of the xAPICs also used a >>> similar principle. >> I certainly have never seen a system on which the APIC has been mapped >> cacheable. I would be very interested in the details, so if you could >> elaborate that would be extremely useful. > > Not really ... I just remember when the SAPIC and later the xAPIC > details were published as novel nearly a decade ago, I remember saying > that some of the voyager interrupt controllers had been using a similar > method for years. > Well, I just looked up the xAPIC spec, and it states very clearly: APIC registers are memory-mapped to a 4-KByte region of the processor’s physical address space with an initial starting address of FEE00000H. For correct APIC operation, this address space must be mapped to an area of memory that has been designated as strong uncacheable (UC). See Section 10.3, “Methods of Caching Available.” So any use of cacheline-related bus cycles is generated by the LAPIC and doesn't affect the CPU <-> LAPIC interface. -hpa