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Date: Mon, 28 Apr 2008 12:59:15 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Arjan van de Ven <arjan@infradead.org>
CC: James Bottomley <James.Bottomley@HansenPartnership.com>,
       Jeff Garzik <jeff@garzik.org>, Ingo Molnar <mingo@elte.hu>,
       Thomas Gleixner <tglx@linutronix.de>,
       linux-kernel <linux-kernel@vger.kernel.org>,
       "David S. Miller" <davem@davemloft.net>,
       Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [patch] x86, voyager: fix ioremap_nocache()
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Arjan van de Ven wrote:
> 
> Cached means that the cpu, at any time, can do a speculative read to the memory.
> It also means that the cpu can then write the speculated cacheline back at any time later,
> if some speculation was going to write to the cacheline but didn't actually happen.
> (before you think this is bogus, at least AMD cpus do this and I can't vouch for Intel
> cpus never doing this).
> If the on-the-bus hardware *ever* writes to the memory without being part of the full
> cache coherence protocol it's in trouble. Big time.
> Even if it sends an invalidate first (which PCI and others just don't allow, not sure about MCA though),
> it's not enough because the cpu can just read it right back... one needs a "take for ownership" not
> an "invalidate" for this to work, and that means being part of the full protocol.
> 

Although realistically speaking, the OS *can* generally know that the 
only transactor is the CPU -- in fact, that will be the normal condition.

	-hpa