From: "H. Peter Anvin" <hpa@zytor.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Roland Dreier <rdreier@cisco.com>, "Moore\,
Eric" <Eric.Moore@lsi.com>,
linux-kernel@vger.kernel.org
Subject: Re: HELP: Is writeq an atomic operation??
Date: Sat, 03 May 2008 10:40:34 -0700 [thread overview]
Message-ID: <481CA392.2080602@zytor.com> (raw)
In-Reply-To: <20080503153521.1d6705cd@core>
Alan Cox wrote:
>>> I don't have an authoritative answer, but I can say that I coded
>>> drivers/infiniband/hw/mthca and .../mlx4 assuming that writeq() is
>>> atomic in the sense that you say, and no one has reported any problems.
>>>
>> If you're not under lock you're screwed on a 32-bit platform.
>
> So what cycles does an MMX, SSE or double float store generate on the
> bus ?
>
Those do generate 64-bit stores; it's just *really* expensive to do it
in the kernel. I have used that trick to test 64-bit hardware in a
32-bit only system, though.
-hpa
next prev parent reply other threads:[~2008-05-03 17:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-02 22:40 HELP: Is writeq an atomic operation?? Moore, Eric
2008-05-02 22:46 ` Roland Dreier
2008-05-03 0:42 ` H. Peter Anvin
2008-05-03 14:35 ` Alan Cox
2008-05-03 17:40 ` H. Peter Anvin [this message]
2008-05-03 22:37 ` Benjamin Herrenschmidt
2008-05-04 17:01 ` Roland Dreier
2008-05-02 22:50 ` Andi Kleen
2008-05-02 23:03 ` Moore, Eric
2008-05-02 23:13 ` Andi Kleen
2008-05-02 23:04 ` Roland Dreier
2008-05-02 23:20 ` Moore, Eric
2008-05-03 0:10 ` Roland Dreier
2008-05-02 23:12 ` Jesse Barnes
2008-05-03 0:41 ` H. Peter Anvin
[not found] <0631C836DBF79F42B5A60C8C8D4E822901047B1D@NAMAIL2.ad.lsil.com>
2008-05-02 22:32 ` David Miller
2008-05-02 22:43 ` Roland Dreier
2008-05-02 22:49 ` David Miller
2008-05-02 22:49 ` Moore, Eric
2008-05-02 22:53 ` Roland Dreier
2008-05-02 23:13 ` Moore, Eric
2008-05-02 23:21 ` Roland Dreier
2008-05-02 23:31 ` Moore, Eric
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