From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDA2EC433FE for ; Tue, 11 Oct 2022 08:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbiJKIAA (ORCPT ); Tue, 11 Oct 2022 04:00:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229620AbiJKH76 (ORCPT ); Tue, 11 Oct 2022 03:59:58 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CC8C1836A for ; Tue, 11 Oct 2022 00:59:55 -0700 (PDT) Received: from p5b127dea.dip0.t-ipconnect.de ([91.18.125.234] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oiAB5-0007Ol-7T; Tue, 11 Oct 2022 09:59:51 +0200 From: Heiko Stuebner To: Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Cc: Anup Patel , Arnd Bergmann , Anup Patel , linux-kernel@vger.kernel.org, Heinrich Schuchardt , Atish Patra , linux-riscv@lists.infradead.org, Nikita Shubin , Anup Patel Subject: Re: [PATCH v2] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Date: Tue, 11 Oct 2022 09:59:50 +0200 Message-ID: <4820619.CvnuH1ECHv@phil> In-Reply-To: <20220727043829.151794-1-apatel@ventanamicro.com> References: <20220727043829.151794-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, 27. Juli 2022, 06:38:29 CEST schrieb Anup Patel: > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > > Signed-off-by: Anup Patel > Reviewed-by: Heinrich Schuchardt > Tested-by: Nikita Shubin Reviewed-by: Heiko Stuebner [on Qemu and Allwinner D1] Tested-by: Heiko Stuebner