Re: 2.6.25.2 - Jiffies/Time jumping back and forth (Regereesion from 2.6.24)

Mike Galbraith
2008-05-08T17:31:48Z

On Thu, 2008-05-08 at 16:13 +0200, Thomas Gleixner wrote:
> On Thu, 8 May 2008, Martin Knoblauch wrote:
> > on two different systems running 2.6.25.2:
> >
> > ibm x3650(2xDualCore)
> > -------------------------------------
> > [root@lpsdm60 ~]# cat /sys/devices/system/clocksource/clocksource0/available_clocksource
> > tsc hpet acpi_pm jiffies
> > [root@lpsdm60 ~]# cat /sys/devices/system/clocksource/clocksource0/current_clocksource
> > tsc
> >
> > HP Proliant DL-380G4 (2xSingleCore)
> > ------------------------------------------------------------
> > [root@lpsdm52 ~]# cat /sys/devices/system/clocksource/clocksource0/available_clocksource
> > tsc hpet acpi_pm jiffies
> > [root@lpsdm52 ~]# cat /sys/devices/system/clocksource/clocksource0/current_clocksource
> > tsc
> >
> > and on the DL380G4 running 2.6.24:
> > ---------------------------------------------------------
> > [root@lpsdm52 ~]# cat /sys/devices/system/clocksource/clocksource0/available_clocksource
> > hpet acpi_pm jiffies tsc
> > [root@lpsdm52 ~]# cat /sys/devices/system/clocksource/clocksource0/current_clocksource
> > hpet
>
> So on 2.6.24 the TSC is declared unstable at some point and 2.6.25
> thinks it works fine. Is this the same kernel config (aside of the 24/25 fuzz) ?

I had a problem with my P4's tsc being declared unstable after S2R. I
carry this patchlet (it's in mainline) in my 2.6.24 kernels to keep the
TSC operational. (browsing, dunno if it's the same problem, but it
might be..)

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 9125efe..05d8f25 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -129,24 +129,24 @@ void __cpuinit check_tsc_sync_source(int cpu)
while (atomic_read(&stop_count) != cpus-1)
cpu_relax();

- /*
- * Reset it - just in case we boot another CPU later:
- */
- atomic_set(&start_count, 0);
-
if (nr_warps) {
printk("\n");
printk(KERN_WARNING "Measured %Ld cycles TSC warp between CPUs,"
" turning off TSC clock.\n", max_warp);
mark_tsc_unstable("check_tsc_sync_source failed");
- nr_warps = 0;
- max_warp = 0;
- last_tsc = 0;
} else {
printk(" passed.\n");
}

/*
+ * Reset it - just in case we boot another CPU later:
+ */
+ atomic_set(&start_count, 0);
+ nr_warps = 0;
+ max_warp = 0;
+ last_tsc = 0;
+
+ /*
* Let the target continue with the bootup:
*/
atomic_inc(&stop_count);