APIC: enable workaround on AMD Fam10h CPUs

APIC: enable workaround on AMD Fam10h CPUs

[Borislav Petkov]

From: Borislav Petkov <borislav.petkov@amd.com>
Date: Tue, 3 Feb 2009 16:24:22 +0100
Subject: [PATCH] APIC: enable workaround on AMD Fam10h CPUs

Impact: fix to enable APIC for AMD Fam10h on chipsets with a missing/b0rked
	ACPI MP table (MADT)

Booting a 32bit kernel on an AMD Fam10h CPU running on chipsets with
missing/b0rked MP table leads to a hang pretty early in the boot process
due to the APIC not being initialized. Fix that by falling back to the
default APIC base address in 32bit code, as it is done in the 64bit
codepath.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
 arch/x86/kernel/apic.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index 4b6df24..115449f 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -1436,7 +1436,7 @@ static int __init detect_init_APIC(void)
 	switch (boot_cpu_data.x86_vendor) {
 	case X86_VENDOR_AMD:
 		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
-		    (boot_cpu_data.x86 == 15))
+		    (boot_cpu_data.x86 >= 15))
 			break;
 		goto no_apic;
 	case X86_VENDOR_INTEL:
-- 
1.6.0.4

-- 
Regards/Gruss,
Boris.

Operating | Advanced Micro Devices GmbH
  System  | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. München, Germany
 Research | Geschäftsführer: Jochen Polster, Thomas M. McCoy, Giuliano Meroni
  Center  | Sitz: Dornach, Gemeinde Aschheim, Landkreis München
  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: APIC: enable workaround on AMD Fam10h CPUs

[H. Peter Anvin]

Borislav Petkov wrote:
> From: Borislav Petkov <borislav.petkov@amd.com>
> Date: Tue, 3 Feb 2009 16:24:22 +0100
> Subject: [PATCH] APIC: enable workaround on AMD Fam10h CPUs

Applied to tip:x86/urgent.

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

Re: APIC: enable workaround on AMD Fam10h CPUs

[Mark Hounschell]

Borislav Petkov wrote:
> From: Borislav Petkov <borislav.petkov@amd.com>
> Date: Tue, 3 Feb 2009 16:24:22 +0100
> Subject: [PATCH] APIC: enable workaround on AMD Fam10h CPUs
> 
> Impact: fix to enable APIC for AMD Fam10h on chipsets with a missing/b0rked
> 	ACPI MP table (MADT)
> 
> Booting a 32bit kernel on an AMD Fam10h CPU running on chipsets with
> missing/b0rked MP table leads to a hang pretty early in the boot process
> due to the APIC not being initialized. Fix that by falling back to the
> default APIC base address in 32bit code, as it is done in the 64bit
> codepath.
> 
> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> ---
>  arch/x86/kernel/apic.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
> index 4b6df24..115449f 100644
> --- a/arch/x86/kernel/apic.c
> +++ b/arch/x86/kernel/apic.c
> @@ -1436,7 +1436,7 @@ static int __init detect_init_APIC(void)
>  	switch (boot_cpu_data.x86_vendor) {
>  	case X86_VENDOR_AMD:
>  		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
> -		    (boot_cpu_data.x86 == 15))
> +		    (boot_cpu_data.x86 >= 15))
>  			break;
>  		goto no_apic;
>  	case X86_VENDOR_INTEL:

Hi Borislav,

Could this have anything to do with my Phenom-II problem that you've been so kind
to help me with?

Thanks
Mark

Re: APIC: enable workaround on AMD Fam10h CPUs

[Borislav Petkov]

On Wed, Feb 04, 2009 at 07:41:12AM -0500, Mark Hounschell wrote:
> Borislav Petkov wrote:
> > From: Borislav Petkov <borislav.petkov@amd.com>
> > Date: Tue, 3 Feb 2009 16:24:22 +0100
> > Subject: [PATCH] APIC: enable workaround on AMD Fam10h CPUs
> > 
> > Impact: fix to enable APIC for AMD Fam10h on chipsets with a missing/b0rked
> > 	ACPI MP table (MADT)
> > 
> > Booting a 32bit kernel on an AMD Fam10h CPU running on chipsets with
> > missing/b0rked MP table leads to a hang pretty early in the boot process
> > due to the APIC not being initialized. Fix that by falling back to the
> > default APIC base address in 32bit code, as it is done in the 64bit
> > codepath.
> > 
> > Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> > ---
> >  arch/x86/kernel/apic.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
> > index 4b6df24..115449f 100644
> > --- a/arch/x86/kernel/apic.c
> > +++ b/arch/x86/kernel/apic.c
> > @@ -1436,7 +1436,7 @@ static int __init detect_init_APIC(void)
> >  	switch (boot_cpu_data.x86_vendor) {
> >  	case X86_VENDOR_AMD:
> >  		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
> > -		    (boot_cpu_data.x86 == 15))
> > +		    (boot_cpu_data.x86 >= 15))
> >  			break;
> >  		goto no_apic;
> >  	case X86_VENDOR_INTEL:
> 
> Hi Borislav,
> 
> Could this have anything to do with my Phenom-II problem that you've been so kind
> to help me with?
> 
> Thanks
> Mark
>

Well, we thought so originally but since a 64bit kernel fails booting
on your machine too, it can't be it because this is a 32bit codepath
issue.

Another question: does your machine boot a tickless kernel (CONFIG_NO_HZ enabled)?

-- 
Regards/Gruss,
Boris.

Operating | Advanced Micro Devices GmbH
  System  | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. München, Germany
 Research | Geschäftsführer: Jochen Polster, Thomas M. McCoy, Giuliano Meroni
  Center  | Sitz: Dornach, Gemeinde Aschheim, Landkreis München
  (OSRC)  | Registergericht München, HRB Nr. 43632