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* pci express bar over 4gb
@ 2009-03-11 13:28 protagora27 protagora27
  2009-03-12  0:01 ` Robert Hancock
  0 siblings, 1 reply; 3+ messages in thread
From: protagora27 protagora27 @ 2009-03-11 13:28 UTC (permalink / raw)
  To: linux-kernel

Hello Folks,

I have intel desktop board dx48bt2. I'm developing sw under linux
2.6.24  x86_64  for a pci express card ( pci express 2.0 compliant).
I have to setup pci bar over 4 gb but bios uses value e0000000 as base
address for pcie boards.
I have seen that pciexbar is a register ( x48 chipset)  that decides
where pcie boards are mapped inside memory map.
My goal is rewriting pcibar 0 e pcibar 1 with a value above 4gb. Maybe
 I have  to rewrite pciexbar and then rewrite pci bar in my board.
Questions:
1) can I rewrite  pciexbar  and where ?
2) can i rewrite pcibar 0 and 1 with a value over 4 gb
3) If i change bar 0 and bar 1 after linux startup have i to use hotplugging ?

Thanks

Luca

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: pci express bar over 4gb
  2009-03-11 13:28 pci express bar over 4gb protagora27 protagora27
@ 2009-03-12  0:01 ` Robert Hancock
       [not found]   ` <5b9cce670903120205yfd0cc5cp203059299877124@mail.gmail.com>
  0 siblings, 1 reply; 3+ messages in thread
From: Robert Hancock @ 2009-03-12  0:01 UTC (permalink / raw)
  To: protagora27 protagora27; +Cc: linux-kernel

protagora27 protagora27 wrote:
> Hello Folks,
> 
> I have intel desktop board dx48bt2. I'm developing sw under linux
> 2.6.24  x86_64  for a pci express card ( pci express 2.0 compliant).
> I have to setup pci bar over 4 gb but bios uses value e0000000 as base
> address for pcie boards.
> I have seen that pciexbar is a register ( x48 chipset)  that decides
> where pcie boards are mapped inside memory map.

No, the PCIEXBAR register controls where the MMCONFIG aperture is mapped 
in memory. (It's a rather unfortunate name, I think, as it doesn't 
really have anything to do with PCI Express other than that you need to 
use MMCONFIG to access PCI Express extended configuration space).

> My goal is rewriting pcibar 0 e pcibar 1 with a value above 4gb. Maybe
>  I have  to rewrite pciexbar and then rewrite pci bar in my board.
> Questions:
> 1) can I rewrite  pciexbar  and where ?
> 2) can i rewrite pcibar 0 and 1 with a value over 4 gb
> 3) If i change bar 0 and bar 1 after linux startup have i to use hotplugging ?
> 
> Thanks
> 
> Luca


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: pci express bar over 4gb
       [not found]   ` <5b9cce670903120205yfd0cc5cp203059299877124@mail.gmail.com>
@ 2009-03-12 14:44     ` Robert Hancock
  0 siblings, 0 replies; 3+ messages in thread
From: Robert Hancock @ 2009-03-12 14:44 UTC (permalink / raw)
  To: protagora27 protagora27; +Cc: linux-kernel

protagora27 protagora27 wrote:
> 2009/3/12 Robert Hancock <hancockrwd@gmail.com>:
>> protagora27 protagora27 wrote:
>>> Hello Folks,
>>>
>>> I have intel desktop board dx48bt2. I'm developing sw under linux
>>> 2.6.24  x86_64  for a pci express card ( pci express 2.0 compliant).
>>> I have to setup pci bar over 4 gb but bios uses value e0000000 as base
>>> address for pcie boards.
>>> I have seen that pciexbar is a register ( x48 chipset)  that decides
>>> where pcie boards are mapped inside memory map.
> But if  I see /proc/iomem:
> 
> 00000000-0009bfff : System RAM
> 0009c000-0009ffff : reserved
> 000c0000-000dffff : pnp 00:01
> 000e0000-000fffff : reserved
> 00100000-ce8fdfff : System RAM
>   00200000-0046f0b4 : Kernel code
>   0046f0b5-005b939f : Kernel data
>   00631000-006ba8c7 : Kernel bss
> ce8fe000-ce982fff : ACPI Non-volatile Storage
> ce983000-cfaf0fff : System RAM
> cfaf1000-cfaf2fff : reserved
> cfaf3000-cfb8afff : System RAM
> cfb8b000-cfbe0fff : ACPI Non-volatile Storage
> cfbe1000-cfbe6fff : System RAM
> cfbe7000-cfbf1fff : ACPI Tables
> cfbf2000-cfbf2fff : System RAM
> cfbf3000-cfbfefff : ACPI Tables
> cfbff000-cfbfffff : System RAM
> cfc00000-cfffffff : reserved
> d0000000-dfffffff : PCI Bus #01
>   d0000000-dfffffff : 0000:01:00.0
> e0000000-e1ffffff : PCI Bus #01
>   e0000000-e0ffffff : 0000:01:00.0
>   e1000000-e1ffffff : 0000:01:00.0
> e2000000-e20fffff : PCI Bus #05
>   e2000000-e2003fff : 0000:05:03.0
>   e2004000-e20047ff : 0000:05:03.0
>     e2004000-e20047ff : ohci1394
> e2100000-e21fffff : PCI Bus #04
>   e2100000-e21003ff : 0000:04:00.0
> e2200000-e22fffff : PCI Bus #02
>   e2200000-e2200fff : 0000:02:00.0
>     e2200000-e2200fff : ycrypto
> e2300000-e231ffff : 0000:00:19.0
>   e2300000-e231ffff : e1000e
> e2320000-e2323fff : 0000:00:1b.0
>   e2320000-e2323fff : ICH HD audio
> e2324000-e2324fff : 0000:00:19.0
>   e2324000-e2324fff : e1000e
> e2325000-e23257ff : 0000:00:1f.2
>   e2325000-e23257ff : ahci
> e2325800-e2325bff : 0000:00:1d.7
>   e2325800-e2325bff : ehci_hcd
> e2325c00-e2325fff : 0000:00:1a.7
>   e2325c00-e2325fff : ehci_hcd
> e2326000-e23260ff : 0000:00:1f.3
> e2400000-e24fffff : PCI Bus #03
> f0000000-f7ffffff : reserved

This f0000000-f7ffffff is likely where PCIEXBAR is pointing to for your 
MMCONFIG aperture.

> feb00000-feb03fff : pnp 00:01
> fec00000-fec00fff : IOAPIC 0
> fed13000-fed13fff : pnp 00:01
> fed14000-fed17fff : pnp 00:01
> fed18000-fed18fff : pnp 00:01
> fed19000-fed19fff : pnp 00:01
> fed1c000-fed1ffff : pnp 00:01
> fed20000-fed3ffff : pnp 00:01
> fed45000-fed99fff : pnp 00:01
> fee00000-fee00fff : Local APIC
> ffe00000-ffffffff : reserved
> 100000000-22fffffff : System RAM
> 
> pcie devices are mapped from 0xe0000000 that is  default value of pciexbar.
> 
> However can i change bars addressess of my pcie card so i can map  it
> over 4 gb ?

Not too sure on that one, honestly. You could modify the BAR addresses 
to do that, but you'd also have to change the kernel's idea of where 
they are as well..

> 
> Thanks
> 
> Luca
> 
> 
> 
> 
>> No, the PCIEXBAR register controls where the MMCONFIG aperture is mapped in
>> memory. (It's a rather unfortunate name, I think, as it doesn't really have
>> anything to do with PCI Express other than that you need to use MMCONFIG to
>> access PCI Express extended configuration space).
>>
>>> My goal is rewriting pcibar 0 e pcibar 1 with a value above 4gb. Maybe
>>>  I have  to rewrite pciexbar and then rewrite pci bar in my board.
>>> Questions:
>>> 1) can I rewrite  pciexbar  and where ?
>>> 2) can i rewrite pcibar 0 and 1 with a value over 4 gb
>>> 3) If i change bar 0 and bar 1 after linux startup have i to use
>>> hotplugging ?
>>>
>>> Thanks
>>>
>>> Luca
>>


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2009-03-12 14:44 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-03-11 13:28 pci express bar over 4gb protagora27 protagora27
2009-03-12  0:01 ` Robert Hancock
     [not found]   ` <5b9cce670903120205yfd0cc5cp203059299877124@mail.gmail.com>
2009-03-12 14:44     ` Robert Hancock

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