From: "H. Peter Anvin" <hpa@zytor.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Tobias Doerffel <tobias.doerffel@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Arjan van de Ven <arjan@infradead.org>,
Suresh Siddha <suresh.b.siddha@intel.com>,
"Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: Specific support for Intel Atom architecture
Date: Thu, 30 Apr 2009 10:03:00 -0700 [thread overview]
Message-ID: <49F9D9C4.8040105@zytor.com> (raw)
In-Reply-To: <20090430154051.GA3346@elte.hu>
Ingo Molnar wrote:
>
> Makes sense. One question would be X86_L1_CACHE_SHIFT - you set it
> to 2^6 == 64 - that's correct i think, most Atoms come with 64 byte
> L2 cache AFAIK.
>
> I've Cc:-ed Intel folks - is this assumption about 64 bytes correct?
>
Seems to be. At least that's what CPUID reports.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
next prev parent reply other threads:[~2009-04-30 17:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-04-30 12:08 Specific support for Intel Atom architecture Tobias Doerffel
2009-04-30 15:40 ` Ingo Molnar
2009-04-30 17:03 ` H. Peter Anvin [this message]
2009-04-30 17:10 ` H. Peter Anvin
2009-05-03 5:38 ` Willy Tarreau
2009-05-03 6:48 ` H. Peter Anvin
2009-05-03 11:08 ` Tobias Doerffel
2009-05-04 13:14 ` Ingo Molnar
2009-05-04 13:32 ` Arjan van de Ven
2009-05-04 17:55 ` Ingo Molnar
2009-05-03 14:53 ` Arjan van de Ven
2009-05-03 18:30 ` Willy Tarreau
2009-05-03 18:37 ` H. Peter Anvin
2009-05-03 19:38 ` Måns Rullgård
2009-05-04 7:22 ` Andi Kleen
2009-05-11 21:30 ` Tobias Doerffel
2009-05-12 6:53 ` Andi Kleen
2009-05-12 14:20 ` Ulrich Drepper
2009-05-12 15:04 ` Andi Kleen
2009-05-12 17:45 ` Ulrich Drepper
2009-05-12 18:13 ` Andi Kleen
2009-05-14 5:04 ` Harvey Harrison
2009-05-14 13:38 ` Ulrich Drepper
2009-05-14 14:01 ` Andi Kleen
2009-05-14 16:19 ` Ulrich Drepper
2009-05-14 17:29 ` Andi Kleen
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