[git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[Jaswinder Singh Rajput]

Complete log is available at:
http://git.kernel.org/?p=linux/kernel/git/jaswinder/linux-2.6-cpu.git;a=shortlog;h=x86/cpufeature

The following changes since commit 3e0c373749d7eb5b354ac0b043f2b2cdf84eefef:
  Yinghai Lu (1):
        x86: clean up and fix setup_clear/force_cpu_cap handling

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/jaswinder/linux-2.6-cpu.git x86/cpufeature

Jaswinder Singh Rajput (15):
      x86: Add cpufeature for Processor Name
      x86: Add cpufeatures for Advanced Power Management
      x86: Add cpufeature for Microcode update
      x86: Add cpufeature for Cache MSRs
      x86: Add cpufeature for Hard and Soft Poweron configuration
      x86: Add cpufeature for Scaleable bus speed
      x86: Add cpufeature for Miscellaneous Features
      x86: Add cpufeature for Platform feature
      x86: Add cpufeature for Hardware configuration
      x86: Add cpufeature for System configuration
      x86: Add cpufeature for System management mode (SMM)
      x86: Add cpufeature for MM configuration
      x86: Add cpufeature for Bus configuration
      x86: Add cpufeature for performance frequency APERF/MPERF
      x86: Add cpufeature for ancient performance monitoring

 arch/x86/include/asm/cpufeature.h          |   35 ++++++++--
 arch/x86/include/asm/processor.h           |    1 -
 arch/x86/kernel/cpu/Makefile               |    2 +-
 arch/x86/kernel/cpu/amd.c                  |   35 +++++++---
 arch/x86/kernel/cpu/common.c               |   17 ++++-
 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c |    9 +--
 arch/x86/kernel/cpu/intel.c                |  106 ++++++++++++++++++++++++----
 arch/x86/kernel/cpu/powerflags.c           |   20 -----
 arch/x86/kernel/cpu/proc.c                 |   14 ----
 arch/x86/kernel/microcode_amd.c            |    3 +
 arch/x86/kernel/microcode_intel.c          |    3 +
 11 files changed, 172 insertions(+), 73 deletions(-)
 delete mode 100644 arch/x86/kernel/cpu/powerflags.c

complete diff:

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..f660e99 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS	10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,6 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -153,8 +152,24 @@
  * Auxiliary flags: Linux defined - For features scattered in various
  * CPUID levels like 0x6, 0xA etc
  */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
+#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
+#define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
+#define X86_FEATURE_CACHE	(7*32+ 4) /* BBL_CR_* MSRs (PII & PIII)	*/
+#define X86_FEATURE_CACHE_CTL	(7*32+ 5) /* Cache control MSRs		*/
+#define X86_FEATURE_HARD_POWERON (7*32+ 6) /* Hard Poweron configuration*/
+#define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
+#define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
+#define X86_FEATURE_MISC 	(7*32+ 9) /* Miscellaneous features	*/
+#define X86_FEATURE_PLATFORM 	(7*32+ 10) /* Platform feature		*/
+#define X86_FEATURE_HW_CFG 	(7*32+ 11) /* Hardware configuration	*/
+#define X86_FEATURE_SYS_CFG 	(7*32+ 12) /* System configuration	*/
+#define X86_FEATURE_SMM 	(7*32+ 13) /* System Management	Mode	*/
+#define X86_FEATURE_MM_CFG 	(7*32+ 14) /* MM configuration		*/
+#define X86_FEATURE_BUS_CFG 	(7*32+ 15) /* Bus configuration		*/
+#define X86_FEATURE_PERF_FREQ 	(7*32+ 16) /* Performance frequency	*/
+#define X86_FEATURE_PERFMON 	(7*32+ 17) /* Performance monitoring	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -163,12 +178,22 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx */
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperatue sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
 
 extern const char * const x86_cap_flags[NCAPINTS*32];
-extern const char * const x86_power_flags[32];
 
 #define test_cpu_cap(c, bit)						\
 	 test_bit(bit, (unsigned long *)((c)->x86_capability))
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index fed93fe..163b447 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -90,7 +90,6 @@ struct cpuinfo_x86 {
 	/* in KB - valid for CPUS which support this call: */
 	int			x86_cache_size;
 	int			x86_cache_alignment;	/* In bytes */
-	int			x86_power;
 	unsigned long		loops_per_jiffy;
 #ifdef CONFIG_SMP
 	/* cpus sharing the last level cache: */
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 4e242f9..3e5da32 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -8,7 +8,7 @@ CFLAGS_REMOVE_common.o = -pg
 endif
 
 obj-y			:= intel_cacheinfo.o addon_cpuid_features.o
-obj-y			+= proc.o capflags.o powerflags.o common.o
+obj-y			+= proc.o capflags.o common.o
 obj-y			+= vmware.o hypervisor.o
 
 obj-$(CONFIG_X86_32)	+= bugs.o cmpxchg.o
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7e4a459..849d794 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -333,15 +333,6 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 {
 	early_init_amd_mc(c);
 
-	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states
-	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-	}
-
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
 #else
@@ -485,6 +476,32 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		}
 	}
 #endif
+
+	/* Set cpufeatures for miscellaneous MSRs			*/
+	if (c->x86 >= 7) {				/* K7+		*/
+		/* MSRC001_0015 Hardware Configuration Register (HWCR)	*/
+		set_cpu_cap(c, X86_FEATURE_HW_CFG);
+		/* Performance monitoring support			*/
+		set_cpu_cap(c, X86_FEATURE_PERFMON);
+	}
+	if (c->x86 >= 8) {				/* K8+		*/
+		/*
+		 * System configuration MSRs:
+		 * MSRC001_0010 System Configuration Register (SYS_CFG)
+		 * MSRC001_001F Northbridge Configuration Register (NB_CFG)
+		 */
+		set_cpu_cap(c, X86_FEATURE_SYS_CFG);
+		/* SMM MSRs C001_0111-C001_0113 & C001_0050-C000_0056	*/
+		set_cpu_cap(c, X86_FEATURE_SMM);
+	}
+	if (c->x86 >= 0x10) {				/* fam10h+	*/
+		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
+		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+		/* MSRC001_0058 MMIO Configuration Base Address Register*/
+		set_cpu_cap(c, X86_FEATURE_MM_CFG);
+		/* MSRC001_1023 Bus Unit Configuration Register (BU_CFG)*/
+		set_cpu_cap(c, X86_FEATURE_BUS_CFG);
+	}
 }
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e7fd5c4..511a970 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -360,6 +360,7 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 	c->x86_model_id[48] = 0;
+	set_cpu_cap(c, X86_FEATURE_PNAME);
 
 	/*
 	 * Intel chips right-justify this string for some dumb reason;
@@ -575,8 +576,22 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 #endif
 
 	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
+		c->x86_capability[9] = cpuid_edx(0x80000007);
 
+	/*
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states.
+	 *
+	 * It is also reliable across cores and sockets. (but not across
+	 * cabinets - we turn it off in that case explicitly.)
+	 */
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
+		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
+		if (c->x86_vendor == X86_VENDOR_INTEL)
+			sched_clock_stable = 1;
+	}
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 208ecf6..3811ca6 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -60,7 +60,6 @@ enum {
 };
 
 #define INTEL_MSR_RANGE		(0xffff)
-#define CPUID_6_ECX_APERFMPERF_CAPABILITY	(0x1)
 
 struct acpi_cpufreq_data {
 	struct acpi_processor_performance *acpi_data;
@@ -735,12 +734,8 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
 	acpi_processor_notify_smm(THIS_MODULE);
 
 	/* Check for APERF/MPERF support in hardware */
-	if (c->x86_vendor == X86_VENDOR_INTEL && c->cpuid_level >= 6) {
-		unsigned int ecx;
-		ecx = cpuid_ecx(6);
-		if (ecx & CPUID_6_ECX_APERFMPERF_CAPABILITY)
-			acpi_cpufreq_driver.getavg = get_measured_perf;
-	}
+	if (cpu_has(c, X86_FEATURE_PERF_FREQ))
+		acpi_cpufreq_driver.getavg = get_measured_perf;
 
 	dprintk("CPU%u - ACPI performance management activated.\n", cpu);
 	for (i = 0; i < perf->state_count; i++)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7437fa1..e3ce8c6 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,20 +61,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
-	 *
-	 * It is also reliable across cores and sockets. (but not across
-	 * cabinets - we turn it off in that case explicitly.)
-	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
-		sched_clock_stable = 1;
-	}
-
-	/*
 	 * There is a known erratum on Pentium III and Core Solo
 	 * and Core Duo CPUs.
 	 * " Page with PAT set to WC while associated MTRR is UC
@@ -324,7 +310,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 		/* Check for version and the number of counters */
 		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
-	}
+	} else if (c->x86 >= 5)
+		/* ancient performance monitoring support */
+		set_cpu_cap(c, X86_FEATURE_PERFMON);
 
 	if (cpu_has_xmm2)
 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
@@ -404,6 +392,94 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 	if (cpu_has(c, X86_FEATURE_VMX))
 		detect_vmx_virtcap(c);
+
+	/* Set cpufeatures for miscellaneous MSRs			*/
+	if (c->x86 == 6) {
+		/* Miscellaneous Features IA32_MISC_ENABLE		*/
+		set_cpu_cap(c, X86_FEATURE_MISC);
+
+		switch (c->x86_model) {
+		case 1:					/* Pentium Pro	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* !Miscellaneous Features IA32_MISC_ENABLE	*/
+			clear_cpu_cap(c, X86_FEATURE_MISC);
+			break;
+
+		case 3: case 5:				/* Pentium II	*/
+		case 7: case 8: case 0xA: case 0xB:	/* Pentium III	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* BBL_CR_* MSRs (Pentium II & III processors)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			/* !Miscellaneous Features IA32_MISC_ENABLE	*/
+			clear_cpu_cap(c, X86_FEATURE_MISC);
+			break;
+
+		case 9:	case 0xD:			/* Pentium M	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			break;
+
+		case 0xE:				/* Core		*/
+		case 0xF: case 0x17:			/* Core 2	*/
+		case 0x1C:				/* ATOM		*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			/* Scaleable bus speed MSR_FSB_FREQ		*/
+			set_cpu_cap(c, X86_FEATURE_FSB_FREQ);
+			break;
+
+		case 0x16:				/* Celeron Core	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			break;
+
+		case 0x1D:				/* Xeon MP	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/*
+			 * Soft Poweron configuration MSR_EBC_SOFT_POWERON
+			 * Frequency configuration MSR_EBC_FREQUENCY_ID
+			 */
+			set_cpu_cap(c, X86_FEATURE_SOFT_POWERON);
+			break;
+		}
+	}
+	if (c->x86 == 0xF) {
+		/* Hard Poweron configuration MSR_EBL_CR_POWERON	*/
+		set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+		/*
+		 * Soft Poweron configuration MSR_EBC_SOFT_POWERON
+		 * Frequency configuration MSR_EBC_FREQUENCY_ID
+		 */
+		set_cpu_cap(c, X86_FEATURE_SOFT_POWERON);
+
+		/* Miscellaneous Features IA32_MISC_ENABLE		*/
+		set_cpu_cap(c, X86_FEATURE_MISC);
+
+		switch (c->x86_model) {
+		case 3: case 4: case 6:
+			/* Platform Feature MSR_PLATFORM_BRV		*/
+			set_cpu_cap(c, X86_FEATURE_PLATFORM);
+			break;
+		}
+	}
+	if (c->cpuid_level >= 6) {
+		/*
+		 * Hardware Coordination Feedback Capability
+		 * (Presence of IA32_APERF, IA32_MPERF MSRs)
+		 */
+		l2 = cpuid_ecx(6);
+		if (l2 & 1)
+			set_cpu_cap(c, X86_FEATURE_PERF_FREQ);
+	}
 }
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerflags.c
deleted file mode 100644
index 5abbea2..0000000
--- a/arch/x86/kernel/cpu/powerflags.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Strings for the various x86 power flags
- *
- * This file must not contain any executable code.
- */
-
-#include <asm/cpufeature.h>
-
-const char *const x86_power_flags[32] = {
-	"ts",	/* temperature sensor */
-	"fid",  /* frequency id control */
-	"vid",  /* voltage id control */
-	"ttp",  /* thermal trip */
-	"tm",
-	"stc",
-	"100mhzsteps",
-	"hwpstate",
-	"",	/* tsc invariant mapped to constant_tsc */
-		/* nothing */
-};
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index f93047f..523bf39 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -121,20 +121,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
 		   c->x86_phys_bits, c->x86_virt_bits);
 #endif
-
-	seq_printf(m, "power management:");
-	for (i = 0; i < 32; i++) {
-		if (c->x86_power & (1 << i)) {
-			if (i < ARRAY_SIZE(x86_power_flags) &&
-			    x86_power_flags[i])
-				seq_printf(m, "%s%s",
-					   x86_power_flags[i][0]?" ":"",
-					   x86_power_flags[i]);
-			else
-				seq_printf(m, " [%d]", i);
-		}
-	}
-
 	seq_printf(m, "\n\n");
 
 	return 0;
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 453b579..ec9e5e2 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -95,6 +95,9 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 		       "supported\n", cpu, c->x86);
 		return -1;
 	}
+	/* setting microcode update feature to friendly access of UCODE MSRs */
+	set_cpu_cap(c, X86_FEATURE_MICROCODE);
+
 	rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
 	printk(KERN_INFO "microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev);
 	return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 149b9ec..2fcaa58 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -168,6 +168,9 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 		return -1;
 	}
 
+	/* setting microcode update feature to friendly access of UCODE MSRs */
+	set_cpu_cap(c, X86_FEATURE_MICROCODE);
+
 	csig->sig = cpuid_eax(0x00000001);
 
 	if ((c->x86_model >= 5) || (c->x86 > 6)) {

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[Robert Richter]

On 11.05.09 21:44:54, Jaswinder Singh Rajput wrote:
> Complete log is available at:
> http://git.kernel.org/?p=linux/kernel/git/jaswinder/linux-2.6-cpu.git;a=shortlog;h=x86/cpufeature
> 
> The following changes since commit 3e0c373749d7eb5b354ac0b043f2b2cdf84eefef:
>   Yinghai Lu (1):
>         x86: clean up and fix setup_clear/force_cpu_cap handling
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/jaswinder/linux-2.6-cpu.git x86/cpufeature
> 
> Jaswinder Singh Rajput (15):
>       x86: Add cpufeature for Processor Name
>       x86: Add cpufeatures for Advanced Power Management
>       x86: Add cpufeature for Microcode update
>       x86: Add cpufeature for Cache MSRs
>       x86: Add cpufeature for Hard and Soft Poweron configuration
>       x86: Add cpufeature for Scaleable bus speed
>       x86: Add cpufeature for Miscellaneous Features
>       x86: Add cpufeature for Platform feature
>       x86: Add cpufeature for Hardware configuration
>       x86: Add cpufeature for System configuration
>       x86: Add cpufeature for System management mode (SMM)
>       x86: Add cpufeature for MM configuration
>       x86: Add cpufeature for Bus configuration
>       x86: Add cpufeature for performance frequency APERF/MPERF
>       x86: Add cpufeature for ancient performance monitoring

Jaswinder,

this is the last time I will mention this.

Please send a patch set with numbered patches. Your pull requests are
hard to review. Even maintainers send their patches this way for
review though the patches are available also in some git
repositories. Make these patches relative to a common tree (linux-2.6
or tip) or the maintainers tree (in this case also tip). Doing so,
others can apply the patches easily in a local repository. This will
reduce the efforts to review and test your patches and you will
probably get more feedback.

Thanks,

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com

[PATCH 1/15 -tip] x86: Add cpufeature for Processor Name

[Jaswinder Singh Rajput]

Processor Name / Brand String (Function 8000_0002h, 8000_0003h, 8000_0004h)
Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to 16 ASCII bytes of the processor name in the EAX, EBX, ECX, and EDX registers.

X86_FEATURE_PNAME will be useful for displaying MSRs like AMD:
MSRC001_00[35:30] Processor Name String Registers

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/common.c      |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..f106cfc 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -155,6 +155,7 @@
  */
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name */
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e7fd5c4..59dd479 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -360,6 +360,7 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 	c->x86_model_id[48] = 0;
+	set_cpu_cap(c, X86_FEATURE_PNAME);
 
 	/*
 	 * Intel chips right-justify this string for some dumb reason;
-- 
1.6.0.6

[PATCH 2/15 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

1. Add Advanced Power Management (Function 8000_0007h), edx
2. unification of X86_FEATURE_CONSTANT_TSC (from intel.c, amd.c to common.c)
3. Remove cpu/powerflags.c
4. Remove x86_power
5. Move 'power management' to flags of /proc/cpuinfo

/proc/cpuinfo (before)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
..
power management: ts ttp tm stc 100mhzsteps hwpstate

/proc/cpuinfo (after)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
ts ttp htc stc 100mhzsteps hwpstate constant_tsc

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |   15 ++++++++++++---
 arch/x86/include/asm/processor.h  |    1 -
 arch/x86/kernel/cpu/Makefile      |    2 +-
 arch/x86/kernel/cpu/amd.c         |    9 ---------
 arch/x86/kernel/cpu/common.c      |   16 +++++++++++++++-
 arch/x86/kernel/cpu/intel.c       |   14 --------------
 arch/x86/kernel/cpu/powerflags.c  |   20 --------------------
 arch/x86/kernel/cpu/proc.c        |   14 --------------
 8 files changed, 28 insertions(+), 63 deletions(-)
 delete mode 100644 arch/x86/kernel/cpu/powerflags.c

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f106cfc..776d12c 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS	10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,6 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -164,12 +163,22 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx */
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperatue sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
 
 extern const char * const x86_cap_flags[NCAPINTS*32];
-extern const char * const x86_power_flags[32];
 
 #define test_cpu_cap(c, bit)						\
 	 test_bit(bit, (unsigned long *)((c)->x86_capability))
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index fed93fe..163b447 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -90,7 +90,6 @@ struct cpuinfo_x86 {
 	/* in KB - valid for CPUS which support this call: */
 	int			x86_cache_size;
 	int			x86_cache_alignment;	/* In bytes */
-	int			x86_power;
 	unsigned long		loops_per_jiffy;
 #ifdef CONFIG_SMP
 	/* cpus sharing the last level cache: */
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 4e242f9..3e5da32 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -8,7 +8,7 @@ CFLAGS_REMOVE_common.o = -pg
 endif
 
 obj-y			:= intel_cacheinfo.o addon_cpuid_features.o
-obj-y			+= proc.o capflags.o powerflags.o common.o
+obj-y			+= proc.o capflags.o common.o
 obj-y			+= vmware.o hypervisor.o
 
 obj-$(CONFIG_X86_32)	+= bugs.o cmpxchg.o
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7e4a459..2c1931f 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -333,15 +333,6 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 {
 	early_init_amd_mc(c);
 
-	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states
-	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-	}
-
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
 #else
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 59dd479..511a970 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -576,8 +576,22 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 #endif
 
 	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
+		c->x86_capability[9] = cpuid_edx(0x80000007);
 
+	/*
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states.
+	 *
+	 * It is also reliable across cores and sockets. (but not across
+	 * cabinets - we turn it off in that case explicitly.)
+	 */
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
+		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
+		if (c->x86_vendor == X86_VENDOR_INTEL)
+			sched_clock_stable = 1;
+	}
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7437fa1..330f42c 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,20 +61,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
-	 *
-	 * It is also reliable across cores and sockets. (but not across
-	 * cabinets - we turn it off in that case explicitly.)
-	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
-		sched_clock_stable = 1;
-	}
-
-	/*
 	 * There is a known erratum on Pentium III and Core Solo
 	 * and Core Duo CPUs.
 	 * " Page with PAT set to WC while associated MTRR is UC
diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerflags.c
deleted file mode 100644
index 5abbea2..0000000
--- a/arch/x86/kernel/cpu/powerflags.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Strings for the various x86 power flags
- *
- * This file must not contain any executable code.
- */
-
-#include <asm/cpufeature.h>
-
-const char *const x86_power_flags[32] = {
-	"ts",	/* temperature sensor */
-	"fid",  /* frequency id control */
-	"vid",  /* voltage id control */
-	"ttp",  /* thermal trip */
-	"tm",
-	"stc",
-	"100mhzsteps",
-	"hwpstate",
-	"",	/* tsc invariant mapped to constant_tsc */
-		/* nothing */
-};
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index f93047f..523bf39 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -121,20 +121,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
 		   c->x86_phys_bits, c->x86_virt_bits);
 #endif
-
-	seq_printf(m, "power management:");
-	for (i = 0; i < 32; i++) {
-		if (c->x86_power & (1 << i)) {
-			if (i < ARRAY_SIZE(x86_power_flags) &&
-			    x86_power_flags[i])
-				seq_printf(m, "%s%s",
-					   x86_power_flags[i][0]?" ":"",
-					   x86_power_flags[i]);
-			else
-				seq_printf(m, " [%d]", i);
-		}
-	}
-
 	seq_printf(m, "\n\n");
 
 	return 0;
-- 
1.6.0.6

[PATCH 3/15 -tip] x86: Add cpufeature for Microcode update

[Jaswinder Singh Rajput]

Setting microcode update feature to friendly access of UCODE MSRs like:
1. IA32_PLATFORM_ID (Intel)
2. IA32_UCODE_WRITE (Intel)
3. IA32_UCODE_REV (Intel)
4. MSR_AMD64_PATCH_LEVEL (AMD)
5. MSR_AMD64_PATCH_LOADER (AMD)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    7 ++++---
 arch/x86/kernel/microcode_amd.c   |    3 +++
 arch/x86/kernel/microcode_intel.c |    3 +++
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 776d12c..06b0919 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -152,9 +152,10 @@
  * Auxiliary flags: Linux defined - For features scattered in various
  * CPUID levels like 0x6, 0xA etc
  */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
-#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name */
+#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
+#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
+#define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 453b579..ec9e5e2 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -95,6 +95,9 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 		       "supported\n", cpu, c->x86);
 		return -1;
 	}
+	/* setting microcode update feature to friendly access of UCODE MSRs */
+	set_cpu_cap(c, X86_FEATURE_MICROCODE);
+
 	rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
 	printk(KERN_INFO "microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev);
 	return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 149b9ec..2fcaa58 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -168,6 +168,9 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 		return -1;
 	}
 
+	/* setting microcode update feature to friendly access of UCODE MSRs */
+	set_cpu_cap(c, X86_FEATURE_MICROCODE);
+
 	csig->sig = cpuid_eax(0x00000001);
 
 	if ((c->x86_model >= 5) || (c->x86 > 6)) {
-- 
1.6.0.6

[PATCH 4/15 -tip] x86: Add cpufeature for Cache MSRs

[Jaswinder Singh Rajput]

X86_FEATURE_CACHE : BBL_CR_* MSRs (Pentium II and Pentium III processors)
X86_FEATURE_CACHE_CTL : Cache control MSRs

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    2 ++
 arch/x86/kernel/cpu/amd.c         |    6 ++++++
 arch/x86/kernel/cpu/intel.c       |   21 +++++++++++++++++++++
 3 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 06b0919..da88aa0 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -156,6 +156,8 @@
 #define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
 #define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
 #define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
+#define X86_FEATURE_CACHE	(7*32+ 4) /* BBL_CR_* MSRs (PII & PIII)	*/
+#define X86_FEATURE_CACHE_CTL	(7*32+ 5) /* Cache control MSRs		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 2c1931f..e2fe8e2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -476,6 +476,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		}
 	}
 #endif
+
+	/* Set cpufeatures for miscellaneous MSRs			*/
+	if (c->x86 >= 0x10) {				/* fam10h+	*/
+		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
+		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+	}
 }
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 330f42c..cb198ed 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -390,6 +390,27 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 	if (cpu_has(c, X86_FEATURE_VMX))
 		detect_vmx_virtcap(c);
+
+	/* Set cpufeatures for miscellaneous MSRs			*/
+	if (c->x86 == 6) {
+		switch (c->x86_model) {
+		case 3: case 5:				/* Pentium II	*/
+		case 7: case 8: case 0xA: case 0xB:	/* Pentium III	*/
+			/* BBL_CR_* MSRs (Pentium II & III processors)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			break;
+
+		case 9:	case 0xD:			/* Pentium M	*/
+		case 0xE:				/* Core		*/
+		case 0xF: case 0x17:			/* Core 2	*/
+		case 0x1C:				/* ATOM		*/
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			break;
+		}
+	}
 }
 
 #ifdef CONFIG_X86_32
-- 
1.6.0.6

[PATCH 5/15 -tip] x86: Add cpufeature for Hard and Soft Poweron configuration

[Jaswinder Singh Rajput]

X86_FEATURE_HARD_POWERON : Hard Poweron configuration MSR_EBL_CR_POWERON

X86_FEATURE_SOFT_POWERON : Soft Poweron configuration MSR_EBC_SOFT_POWERON
                         : Frequency configuration MSR_EBC_FREQUENCY_ID

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    2 ++
 arch/x86/kernel/cpu/intel.c       |   33 +++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index da88aa0..97e54ad 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -158,6 +158,8 @@
 #define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
 #define X86_FEATURE_CACHE	(7*32+ 4) /* BBL_CR_* MSRs (PII & PIII)	*/
 #define X86_FEATURE_CACHE_CTL	(7*32+ 5) /* Cache control MSRs		*/
+#define X86_FEATURE_HARD_POWERON (7*32+ 6) /* Hard Poweron configuration*/
+#define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index cb198ed..239048d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -394,8 +394,15 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 	/* Set cpufeatures for miscellaneous MSRs			*/
 	if (c->x86 == 6) {
 		switch (c->x86_model) {
+		case 1:					/* Pentium Pro	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			break;
+
 		case 3: case 5:				/* Pentium II	*/
 		case 7: case 8: case 0xA: case 0xB:	/* Pentium III	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
 			/* BBL_CR_* MSRs (Pentium II & III processors)	*/
 			set_cpu_cap(c, X86_FEATURE_CACHE);
 			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
@@ -406,11 +413,37 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 		case 0xE:				/* Core		*/
 		case 0xF: case 0x17:			/* Core 2	*/
 		case 0x1C:				/* ATOM		*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
 			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
 			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
 			break;
+
+		case 0x16:				/* Celeron Core	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			break;
+
+		case 0x1D:				/* Xeon MP	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/*
+			 * Soft Poweron configuration MSR_EBC_SOFT_POWERON
+			 * Frequency configuration MSR_EBC_FREQUENCY_ID
+			 */
+			set_cpu_cap(c, X86_FEATURE_SOFT_POWERON);
+			break;
 		}
 	}
+	if (c->x86 == 0xF) {
+		/* Hard Poweron configuration MSR_EBL_CR_POWERON	*/
+		set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+		/*
+		 * Soft Poweron configuration MSR_EBC_SOFT_POWERON
+		 * Frequency configuration MSR_EBC_FREQUENCY_ID
+		 */
+		set_cpu_cap(c, X86_FEATURE_SOFT_POWERON);
+	}
 }
 
 #ifdef CONFIG_X86_32
-- 
1.6.0.6

[PATCH 6/15 -tip] x86: Add cpufeature for Scaleable bus speed

[Jaswinder Singh Rajput]

X86_FEATURE_FSB_FREQ : Scaleable bus speed MSR_FSB_FREQ

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/intel.c       |    8 ++++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 97e54ad..8f789b5 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -160,6 +160,7 @@
 #define X86_FEATURE_CACHE_CTL	(7*32+ 5) /* Cache control MSRs		*/
 #define X86_FEATURE_HARD_POWERON (7*32+ 6) /* Hard Poweron configuration*/
 #define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
+#define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 239048d..aca1c7d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -410,6 +410,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			break;
 
 		case 9:	case 0xD:			/* Pentium M	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			break;
+
 		case 0xE:				/* Core		*/
 		case 0xF: case 0x17:			/* Core 2	*/
 		case 0x1C:				/* ATOM		*/
@@ -417,6 +423,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
 			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
 			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			/* Scaleable bus speed MSR_FSB_FREQ		*/
+			set_cpu_cap(c, X86_FEATURE_FSB_FREQ);
 			break;
 
 		case 0x16:				/* Celeron Core	*/
-- 
1.6.0.6

[PATCH 7/15 -tip] x86: Add cpufeature for Miscellaneous Features

[Jaswinder Singh Rajput]

X86_FEATURE_MISC : Miscellaneous Features IA32_MISC_ENABLE

IA32_MISC_ENABLE is introduces as Arctitectural MSR on 0F_00H,
So enable X86_FEATURE_MISC for Family 6 and 0xF and disabling for P6.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/intel.c       |   10 ++++++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 8f789b5..f9e8a02 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -161,6 +161,7 @@
 #define X86_FEATURE_HARD_POWERON (7*32+ 6) /* Hard Poweron configuration*/
 #define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
 #define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
+#define X86_FEATURE_MISC 	(7*32+ 9) /* Miscellaneous features	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index aca1c7d..f63b151 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -393,10 +393,15 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 	/* Set cpufeatures for miscellaneous MSRs			*/
 	if (c->x86 == 6) {
+		/* Miscellaneous Features IA32_MISC_ENABLE		*/
+		set_cpu_cap(c, X86_FEATURE_MISC);
+
 		switch (c->x86_model) {
 		case 1:					/* Pentium Pro	*/
 			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
 			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* !Miscellaneous Features IA32_MISC_ENABLE	*/
+			clear_cpu_cap(c, X86_FEATURE_MISC);
 			break;
 
 		case 3: case 5:				/* Pentium II	*/
@@ -407,6 +412,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			set_cpu_cap(c, X86_FEATURE_CACHE);
 			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
 			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			/* !Miscellaneous Features IA32_MISC_ENABLE	*/
+			clear_cpu_cap(c, X86_FEATURE_MISC);
 			break;
 
 		case 9:	case 0xD:			/* Pentium M	*/
@@ -451,6 +458,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 		 * Frequency configuration MSR_EBC_FREQUENCY_ID
 		 */
 		set_cpu_cap(c, X86_FEATURE_SOFT_POWERON);
+
+		/* Miscellaneous Features IA32_MISC_ENABLE		*/
+		set_cpu_cap(c, X86_FEATURE_MISC);
 	}
 }
 
-- 
1.6.0.6

[PATCH 8/15 -tip] x86: Add cpufeature for Platform feature

[Jaswinder Singh Rajput]

X86_FEATURE_PLATFORM : Platform Feature MSR_PLATFORM_BRV

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/intel.c       |    7 +++++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f9e8a02..6eb9134 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -162,6 +162,7 @@
 #define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
 #define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
 #define X86_FEATURE_MISC 	(7*32+ 9) /* Miscellaneous features	*/
+#define X86_FEATURE_PLATFORM 	(7*32+ 10) /* Platform feature		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index f63b151..9c8f386 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -461,6 +461,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 		/* Miscellaneous Features IA32_MISC_ENABLE		*/
 		set_cpu_cap(c, X86_FEATURE_MISC);
+
+		switch (c->x86_model) {
+		case 3: case 4: case 6:
+			/* Platform Feature MSR_PLATFORM_BRV		*/
+			set_cpu_cap(c, X86_FEATURE_PLATFORM);
+			break;
+		}
 	}
 }
 
-- 
1.6.0.6

[PATCH 9/15 -tip] x86: Add cpufeature for Hardware configuration

[Jaswinder Singh Rajput]

X86_FEATURE_HW_CFG : MSRC001_0015 Hardware Configuration Register (HWCR)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 6eb9134..13050e9 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -163,6 +163,7 @@
 #define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
 #define X86_FEATURE_MISC 	(7*32+ 9) /* Miscellaneous features	*/
 #define X86_FEATURE_PLATFORM 	(7*32+ 10) /* Platform feature		*/
+#define X86_FEATURE_HW_CFG 	(7*32+ 11) /* Hardware configuration	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e2fe8e2..b2bccd2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -478,6 +478,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 #endif
 
 	/* Set cpufeatures for miscellaneous MSRs			*/
+	if (c->x86 >= 7) {				/* K7+		*/
+		/* MSRC001_0015 Hardware Configuration Register (HWCR)	*/
+		set_cpu_cap(c, X86_FEATURE_HW_CFG);
+	}
 	if (c->x86 >= 0x10) {				/* fam10h+	*/
 		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
 		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
-- 
1.6.0.6

[PATCH 10/15 -tip] x86: Add cpufeature for System configuration

[Jaswinder Singh Rajput]

X86_FEATURE_SYS_CFG (System configuration MSRs) :
 MSRC001_0010 System Configuration Register (SYS_CFG)
 MSRC001_001F Northbridge Configuration Register (NB_CFG)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    8 ++++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13050e9..674493f 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -164,6 +164,7 @@
 #define X86_FEATURE_MISC 	(7*32+ 9) /* Miscellaneous features	*/
 #define X86_FEATURE_PLATFORM 	(7*32+ 10) /* Platform feature		*/
 #define X86_FEATURE_HW_CFG 	(7*32+ 11) /* Hardware configuration	*/
+#define X86_FEATURE_SYS_CFG 	(7*32+ 12) /* System configuration	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index b2bccd2..8a8db1a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -482,6 +482,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		/* MSRC001_0015 Hardware Configuration Register (HWCR)	*/
 		set_cpu_cap(c, X86_FEATURE_HW_CFG);
 	}
+	if (c->x86 >= 8) {				/* K8+		*/
+		/*
+		 * System configuration MSRs:
+		 * MSRC001_0010 System Configuration Register (SYS_CFG)
+		 * MSRC001_001F Northbridge Configuration Register (NB_CFG)
+		 */
+		set_cpu_cap(c, X86_FEATURE_SYS_CFG);
+	}
 	if (c->x86 >= 0x10) {				/* fam10h+	*/
 		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
 		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
-- 
1.6.0.6

[PATCH 11/15 -tip] x86: Add cpufeature for System management mode (SMM)

[Jaswinder Singh Rajput]

X86_FEATURE_SMM : SMM MSRs C001_0111-C001_0113 & C001_0050-C000_0056

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 674493f..e108284 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -165,6 +165,7 @@
 #define X86_FEATURE_PLATFORM 	(7*32+ 10) /* Platform feature		*/
 #define X86_FEATURE_HW_CFG 	(7*32+ 11) /* Hardware configuration	*/
 #define X86_FEATURE_SYS_CFG 	(7*32+ 12) /* System configuration	*/
+#define X86_FEATURE_SMM 	(7*32+ 13) /* System Management	Mode	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8a8db1a..88cac44 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -489,6 +489,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		 * MSRC001_001F Northbridge Configuration Register (NB_CFG)
 		 */
 		set_cpu_cap(c, X86_FEATURE_SYS_CFG);
+		/* SMM MSRs C001_0111-C001_0113 & C001_0050-C000_0056	*/
+		set_cpu_cap(c, X86_FEATURE_SMM);
 	}
 	if (c->x86 >= 0x10) {				/* fam10h+	*/
 		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
-- 
1.6.0.6

[PATCH 12/15 -tip] x86: Add cpufeature for MM configuration

[Jaswinder Singh Rajput]

X86_FEATURE_MM_CFG : MSRC001_0058 MMIO Configuration Base Address Register

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e108284..101d8de 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -166,6 +166,7 @@
 #define X86_FEATURE_HW_CFG 	(7*32+ 11) /* Hardware configuration	*/
 #define X86_FEATURE_SYS_CFG 	(7*32+ 12) /* System configuration	*/
 #define X86_FEATURE_SMM 	(7*32+ 13) /* System Management	Mode	*/
+#define X86_FEATURE_MM_CFG 	(7*32+ 14) /* MM configuration		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 88cac44..d068044 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -495,6 +495,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 	if (c->x86 >= 0x10) {				/* fam10h+	*/
 		/* MSRC001_1022 Data Cache Configuration (DC_CFG)	*/
 		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+		/* MSRC001_0058 MMIO Configuration Base Address Register*/
+		set_cpu_cap(c, X86_FEATURE_MM_CFG);
 	}
 }
 
-- 
1.6.0.6

[PATCH 13/15 -tip] x86: Add cpufeature for Bus configuration

[Jaswinder Singh Rajput]

X86_FEATURE_BUS_CFG : MSRC001_1023 Bus Unit Configuration Register (BU_CFG)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 101d8de..aee0978 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -167,6 +167,7 @@
 #define X86_FEATURE_SYS_CFG 	(7*32+ 12) /* System configuration	*/
 #define X86_FEATURE_SMM 	(7*32+ 13) /* System Management	Mode	*/
 #define X86_FEATURE_MM_CFG 	(7*32+ 14) /* MM configuration		*/
+#define X86_FEATURE_BUS_CFG 	(7*32+ 15) /* Bus configuration		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index d068044..4b7f7dc 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -497,6 +497,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
 		/* MSRC001_0058 MMIO Configuration Base Address Register*/
 		set_cpu_cap(c, X86_FEATURE_MM_CFG);
+		/* MSRC001_1023 Bus Unit Configuration Register (BU_CFG)*/
+		set_cpu_cap(c, X86_FEATURE_BUS_CFG);
 	}
 }
 
-- 
1.6.0.6

[PATCH 14/15 -tip] x86: Add cpufeature for performance frequency APERF/MPERF

[Jaswinder Singh Rajput]

X86_FEATURE_PERF_FREQ : Hardware Coordination Feedback Capability
                        (Presence of IA32_APERF, IA32_MPERF MSRs)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h          |    1 +
 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c |    9 ++-------
 arch/x86/kernel/cpu/intel.c                |    9 +++++++++
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index aee0978..b91cb47 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,7 @@
 #define X86_FEATURE_SMM 	(7*32+ 13) /* System Management	Mode	*/
 #define X86_FEATURE_MM_CFG 	(7*32+ 14) /* MM configuration		*/
 #define X86_FEATURE_BUS_CFG 	(7*32+ 15) /* Bus configuration		*/
+#define X86_FEATURE_PERF_FREQ 	(7*32+ 16) /* Performance frequency	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 208ecf6..3811ca6 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -60,7 +60,6 @@ enum {
 };
 
 #define INTEL_MSR_RANGE		(0xffff)
-#define CPUID_6_ECX_APERFMPERF_CAPABILITY	(0x1)
 
 struct acpi_cpufreq_data {
 	struct acpi_processor_performance *acpi_data;
@@ -735,12 +734,8 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
 	acpi_processor_notify_smm(THIS_MODULE);
 
 	/* Check for APERF/MPERF support in hardware */
-	if (c->x86_vendor == X86_VENDOR_INTEL && c->cpuid_level >= 6) {
-		unsigned int ecx;
-		ecx = cpuid_ecx(6);
-		if (ecx & CPUID_6_ECX_APERFMPERF_CAPABILITY)
-			acpi_cpufreq_driver.getavg = get_measured_perf;
-	}
+	if (cpu_has(c, X86_FEATURE_PERF_FREQ))
+		acpi_cpufreq_driver.getavg = get_measured_perf;
 
 	dprintk("CPU%u - ACPI performance management activated.\n", cpu);
 	for (i = 0; i < perf->state_count; i++)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 9c8f386..9c5169c 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -469,6 +469,15 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			break;
 		}
 	}
+	if (c->cpuid_level >= 6) {
+		/*
+		 * Hardware Coordination Feedback Capability
+		 * (Presence of IA32_APERF, IA32_MPERF MSRs)
+		 */
+		l2 = cpuid_ecx(6);
+		if (l2 & 1)
+			set_cpu_cap(c, X86_FEATURE_PERF_FREQ);
+	}
 }
 
 #ifdef CONFIG_X86_32
-- 
1.6.0.6

[PATCH 15/15 -tip] x86: Add cpufeature for ancient performance monitoring

[Jaswinder Singh Rajput]

X86_FEATURE_ARCH_PERFMON uses almost different MSRs as compare to
ancient performance monitoring, so introduced X86_FEATURE_PERFMON
to friendly access ancient performance monitor MSRs:

X86_FEATURE_PERFMON : performance monitoring for !X86_FEATURE_ARCH_PERFMON

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |    2 ++
 arch/x86/kernel/cpu/intel.c       |    4 +++-
 3 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index b91cb47..f660e99 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -169,6 +169,7 @@
 #define X86_FEATURE_MM_CFG 	(7*32+ 14) /* MM configuration		*/
 #define X86_FEATURE_BUS_CFG 	(7*32+ 15) /* Bus configuration		*/
 #define X86_FEATURE_PERF_FREQ 	(7*32+ 16) /* Performance frequency	*/
+#define X86_FEATURE_PERFMON 	(7*32+ 17) /* Performance monitoring	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4b7f7dc..849d794 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -481,6 +481,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 	if (c->x86 >= 7) {				/* K7+		*/
 		/* MSRC001_0015 Hardware Configuration Register (HWCR)	*/
 		set_cpu_cap(c, X86_FEATURE_HW_CFG);
+		/* Performance monitoring support			*/
+		set_cpu_cap(c, X86_FEATURE_PERFMON);
 	}
 	if (c->x86 >= 8) {				/* K8+		*/
 		/*
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 9c5169c..e3ce8c6 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -310,7 +310,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 		/* Check for version and the number of counters */
 		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
-	}
+	} else if (c->x86 >= 5)
+		/* ancient performance monitoring support */
+		set_cpu_cap(c, X86_FEATURE_PERFMON);
 
 	if (cpu_has_xmm2)
 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-- 
1.6.0.6

Re: [PATCH 2/15 -tip] x86: Add cpufeatures for Advanced Power Management

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> 1. Add Advanced Power Management (Function 8000_0007h), edx
> 2. unification of X86_FEATURE_CONSTANT_TSC (from intel.c, amd.c to common.c)
> 3. Remove cpu/powerflags.c
> 4. Remove x86_power
> 5. Move 'power management' to flags of /proc/cpuinfo
> 
> /proc/cpuinfo (before)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> ..
> power management: ts ttp tm stc 100mhzsteps hwpstate
> 
> /proc/cpuinfo (after)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> ts ttp htc stc 100mhzsteps hwpstate constant_tsc
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>

NAK in the extreme.

This is an incompatible change to a userspace visible API.  The fact 
that power management flags were separate was braindamage in the first 
place, of course, but we don't break established userspace APIs even if 
they're stupid.

	-hpa

Re: [PATCH 2/15 -tip] x86: Add cpufeatures for Advanced Power Management

[Ingo Molnar]

* H. Peter Anvin <hpa@zytor.com> wrote:

> Jaswinder Singh Rajput wrote:
>> 1. Add Advanced Power Management (Function 8000_0007h), edx
>> 2. unification of X86_FEATURE_CONSTANT_TSC (from intel.c, amd.c to common.c)
>> 3. Remove cpu/powerflags.c
>> 4. Remove x86_power
>> 5. Move 'power management' to flags of /proc/cpuinfo
>>
>> /proc/cpuinfo (before)
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
>> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
>> rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
>> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
>> ..
>> power management: ts ttp tm stc 100mhzsteps hwpstate
>>
>> /proc/cpuinfo (after)
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
>> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
>> rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
>> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
>> ts ttp htc stc 100mhzsteps hwpstate constant_tsc
>>
>> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
>
> NAK in the extreme.
>
> This is an incompatible change to a userspace visible API.  The 
> fact that power management flags were separate was braindamage in 
> the first place, of course, but we don't break established 
> userspace APIs even if they're stupid.

Yes, and you pointed it out in an earlier reply.

Jaswinder, as hpa said it before, we only ever extend cpuflags (i.e. 
add new ones mainly, and map new CPUs to the existing flags), but we 
dont change their semantics.

	Ingo

Re: [PATCH 2/15 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Mon, 2009-05-11 at 21:09 +0200, Ingo Molnar wrote:
> * H. Peter Anvin <hpa@zytor.com> wrote:
> 
> > Jaswinder Singh Rajput wrote:
> >> 1. Add Advanced Power Management (Function 8000_0007h), edx
> >> 2. unification of X86_FEATURE_CONSTANT_TSC (from intel.c, amd.c to common.c)
> >> 3. Remove cpu/powerflags.c
> >> 4. Remove x86_power
> >> 5. Move 'power management' to flags of /proc/cpuinfo
> >>
> >> /proc/cpuinfo (before)
> >> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> >> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> >> rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
> >> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> >> ..
> >> power management: ts ttp tm stc 100mhzsteps hwpstate
> >>
> >> /proc/cpuinfo (after)
> >> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> >> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> >> rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
> >> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> >> ts ttp htc stc 100mhzsteps hwpstate constant_tsc
> >>
> >> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> >
> > NAK in the extreme.
> >
> > This is an incompatible change to a userspace visible API.  The 
> > fact that power management flags were separate was braindamage in 
> > the first place, of course, but we don't break established 
> > userspace APIs even if they're stupid.
> 
> Yes, and you pointed it out in an earlier reply.
> 
> Jaswinder, as hpa said it before, we only ever extend cpuflags (i.e. 
> add new ones mainly, and map new CPUs to the existing flags), but we 
> dont change their semantics.
> 

OK, then I will remove from this patch :

 3. Remove cpu/powerflags.c
 4. Remove x86_power
 5. Move 'power management' to flags of /proc/cpuinfo

--
JSR

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> 
> Jaswinder Singh Rajput (15):
>       x86: Add cpufeature for Processor Name
>       x86: Add cpufeatures for Advanced Power Management
>       x86: Add cpufeature for Microcode update
>       x86: Add cpufeature for Cache MSRs
>       x86: Add cpufeature for Hard and Soft Poweron configuration
>       x86: Add cpufeature for Scaleable bus speed
>       x86: Add cpufeature for Miscellaneous Features
>       x86: Add cpufeature for Platform feature
>       x86: Add cpufeature for Hardware configuration
>       x86: Add cpufeature for System configuration
>       x86: Add cpufeature for System management mode (SMM)
>       x86: Add cpufeature for MM configuration
>       x86: Add cpufeature for Bus configuration
>       x86: Add cpufeature for performance frequency APERF/MPERF
>       x86: Add cpufeature for ancient performance monitoring
> 

Overall, I'm rather confused what the point of this is supposed to be. 
There is value to centralizing CPU knowledge, but some of these flags 
are only used in one place, and as far as I can see in several of your 
patches they aren't used *at all*.

If there is no in-kernel user there is absolutely no point to this.

	-hpa

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[Robert Richter]

On 11.05.09 11:15:52, H. Peter Anvin wrote:
> Jaswinder Singh Rajput wrote:
>> Jaswinder Singh Rajput (15):
>>       x86: Add cpufeature for Processor Name
>>       x86: Add cpufeatures for Advanced Power Management
>>       x86: Add cpufeature for Microcode update
>>       x86: Add cpufeature for Cache MSRs
>>       x86: Add cpufeature for Hard and Soft Poweron configuration
>>       x86: Add cpufeature for Scaleable bus speed
>>       x86: Add cpufeature for Miscellaneous Features
>>       x86: Add cpufeature for Platform feature
>>       x86: Add cpufeature for Hardware configuration
>>       x86: Add cpufeature for System configuration
>>       x86: Add cpufeature for System management mode (SMM)
>>       x86: Add cpufeature for MM configuration
>>       x86: Add cpufeature for Bus configuration
>>       x86: Add cpufeature for performance frequency APERF/MPERF
>>       x86: Add cpufeature for ancient performance monitoring
>
> Overall, I'm rather confused what the point of this is supposed to be. 
> There is value to centralizing CPU knowledge, but some of these flags are 
> only used in one place, and as far as I can see in several of your patches 
> they aren't used *at all*.
>
> If there is no in-kernel user there is absolutely no point to this.

>From the pull request subject

 x86: Addition of cpufeatures to friendly access miscellaneous MSRs

I assume this is mainly done for dumping msrs for debugging
purposes. I don't want to start the discussion again if this really
should be done in kernel space. I would rather parse and decode msr
registers in userspace. MSR tables could be easily implemented there.

Anyway, I think this was already decided. So, maybe for debugging we
should simply read the msrs with rdmsr_safe() and use the exception
handler to check if the msr is implemented. This would avoid most of
the otherwise unused cpufeature flags above.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[H. Peter Anvin]

Robert Richter wrote:
> 
> Anyway, I think this was already decided. So, maybe for debugging we
> should simply read the msrs with rdmsr_safe() and use the exception
> handler to check if the msr is implemented. This would avoid most of
> the otherwise unused cpufeature flags above.
> 

For that use, it's probably the right thing to do.

(FWIW, I agree that dumping MSRs in userspace is the right thing to do. 
  This is being heavily discussed on the util-linux-ng list, as far as I 
can tell.)

	-hpa

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[Jaswinder Singh Rajput]

On Mon, 2009-05-11 at 11:15 -0700, H. Peter Anvin wrote:
> Jaswinder Singh Rajput wrote:
> > 
> > Jaswinder Singh Rajput (15):
> >       x86: Add cpufeature for Processor Name
> >       x86: Add cpufeatures for Advanced Power Management
> >       x86: Add cpufeature for Microcode update
> >       x86: Add cpufeature for Cache MSRs
> >       x86: Add cpufeature for Hard and Soft Poweron configuration
> >       x86: Add cpufeature for Scaleable bus speed
> >       x86: Add cpufeature for Miscellaneous Features
> >       x86: Add cpufeature for Platform feature
> >       x86: Add cpufeature for Hardware configuration
> >       x86: Add cpufeature for System configuration
> >       x86: Add cpufeature for System management mode (SMM)
> >       x86: Add cpufeature for MM configuration
> >       x86: Add cpufeature for Bus configuration
> >       x86: Add cpufeature for performance frequency APERF/MPERF
> >       x86: Add cpufeature for ancient performance monitoring
> > 
> 
> Overall, I'm rather confused what the point of this is supposed to be. 
> There is value to centralizing CPU knowledge, but some of these flags 
> are only used in one place, and as far as I can see in several of your 
> patches they aren't used *at all*.
> 
> If there is no in-kernel user there is absolutely no point to this.
> 

The basic point of these patchset is to friendly access miscellaneous
MSRs in kernel and userspace.

Some of these patches are using hardware cpufeature and others are
software.

In kernel some of these MSRs are frequently used and doing checking
before accessing these MSR in various places.

So I think it will be right approach to check in one place and set
related cpufeature and in other places we only need to check cpufeature
and then access MSR.

This patchset is only adding cpufeature. I will release accessing
cpufeatures in upcoming series.

--
JSR

Re: [git-pull -tip] x86: Addition of cpufeatures to friendly access miscellaneous MSRs

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> 
> The basic point of these patchset is to friendly access miscellaneous
> MSRs in kernel and userspace.
> 
> Some of these patches are using hardware cpufeature and others are
> software.
> 
> In kernel some of these MSRs are frequently used and doing checking
> before accessing these MSR in various places.
> 
> So I think it will be right approach to check in one place and set
> related cpufeature and in other places we only need to check cpufeature
> and then access MSR.
> 
> This patchset is only adding cpufeature. I will release accessing
> cpufeatures in upcoming series.
> 

For those that have in-kernel users, this is fine (and valid), but this 
is the wrong order in which to do things, since you patchset doesn't 
verify where those happen.  Rather, it's better to follow each 
cpufeature with its users rather than a batch of producers followed by a 
set of consumers.

Note: I do *not* consider debugfs only consumers to be valid in this 
context.

	-hpa