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From: Tejun Heo <tj@kernel.org>
To: linux-pci@vger.kernel.org, Greg KH <greg@kroah.com>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	towerlexa@gmx.de
Subject: Who's responsible for configuring CLS on a cardbus device?
Date: Tue, 26 May 2009 22:05:08 +0900	[thread overview]
Message-ID: <4A1BE904.8080302@kernel.org> (raw)

Hello,

This is regarding bko#13257.

 http://bugzilla.kernel.org/show_bug.cgi?id=13257

towerlexa@gmx.de was experiencing very slow transfer rate when using a
cardbus sata_sil SATA controller which is known to be sensitive to
cache line size setting.  The reset default is zero and no one
configured it causing poor performance.

This is solvable by simply setting CLS to the correct value but who's
job is it?  For non-hotplug devices, this is configured by the BIOS
(at least on PC), so for hotplug devices I think falls on the lap of
the PCI code but I'm not sure.  If this is something which the
sata_sil driver should be responsible for, is there an established way
to determine the proper CLS value?

Thanks.

-- 
tejun

             reply	other threads:[~2009-05-26 13:05 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-26 13:05 Tejun Heo [this message]
2009-05-26 13:23 ` Who's responsible for configuring CLS on a cardbus device? Alan Cox
2009-05-26 23:44   ` Robert Hancock
2009-05-26 23:51     ` Tejun Heo
2009-05-27  0:19       ` Kenji Kaneshige
2009-05-27 13:32         ` [RFC PATCH] pccard: configure CLS on attach Tejun Heo
2009-05-27 14:03           ` Matthew Wilcox
2009-05-27 23:11             ` Tejun Heo
2009-05-28  6:46               ` Benjamin Herrenschmidt
2009-06-05  5:49           ` Axel Birndt
2009-05-29 16:53   ` Who's responsible for configuring CLS on a cardbus device? Grant Grundler

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