From: "H. Peter Anvin" <hpa@zytor.com>
To: Roland McGrath <roland@redhat.com>
Cc: Petr Tesarik <ptesarik@suse.cz>, Sam Ravnborg <sam@ravnborg.org>,
LKML <linux-kernel@vger.kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Andi Kleen <andi@firstfloor.org>
Subject: Re: [PATCH] x86: clean up vdso-layout.lds.S
Date: Tue, 09 Jun 2009 08:41:46 -0700 [thread overview]
Message-ID: <4A2E82BA.7040905@zytor.com> (raw)
In-Reply-To: <20090609075247.DA95CFC3B2@magilla.sf.frob.com>
Roland McGrath wrote:
>
> You mean this one:
>
> /*
> * Align the actual code well away from the non-instruction data.
> * This is the best thing for the I-cache.
> */
> . = ALIGN(0x100);
>
> Reading the comment might make it obvious that it's intended for optimal
> code alignment. I suspect someone at the time told me 256 is as big as an
> I-cache line was ever likely to get. You could use L1_CACHE_BYTES instead
> I suppose.
>
Most likely 256 was chosen as a compromise between the the
then-documented value for coherency avoidance (128), future-proofing,
and waste.
I don't think we want to use different values on different platforms,
and end up with dramatically different vdsos when they still need to fit
in the same size envelope.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
next prev parent reply other threads:[~2009-06-09 17:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-01 14:05 [PATCH] x86: clean up vdso-layout.lds.S Petr Tesarik
2009-06-05 15:25 ` Petr Tesarik
2009-06-05 16:27 ` Andi Kleen
2009-06-05 16:24 ` H. Peter Anvin
2009-06-09 7:32 ` Petr Tesarik
2009-06-05 20:07 ` Sam Ravnborg
2009-06-09 7:26 ` Petr Tesarik
2009-06-09 7:52 ` Roland McGrath
2009-06-09 7:57 ` Petr Tesarik
2009-06-09 8:09 ` Roland McGrath
2009-06-09 8:29 ` Petr Tesarik
2009-06-09 15:41 ` H. Peter Anvin [this message]
2009-06-09 18:11 ` Sam Ravnborg
2009-06-09 18:16 ` H. Peter Anvin
2009-06-09 19:22 ` Sam Ravnborg
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