Re: [PATCH] x86/i386: make sure stack-protector segment base is cache aligned

Jeremy Fitzhardinge
2009-09-03T20:41:28Z

On 09/03/09 12:47, Eric Dumazet wrote:
> Jeremy Fitzhardinge a écrit :
>
>> The Intel Optimization Reference Guide says:
>>
>> In Intel Atom microarchitecture, the address generation unit
>> assumes that the segment base will be 0 by default. Non-zero
>> segment base will cause load and store operations to experience
>> a delay.
>> - If the segment base isn't aligned to a cache line
>> boundary, the max throughput of memory operations is
>> reduced to one [e]very 9 cycles.
>> [...]
>> Assembly/Compiler Coding Rule 15. (H impact, ML generality)
>> For Intel Atom processors, use segments with base set to 0
>> whenever possible; avoid non-zero segment base address that is
>> not aligned to cache line boundary at all cost.
>>
>> We can't avoid having a non-zero base for the stack-protector segment, but
>> we can make it cache-aligned.
>>
>> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
>>
>> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
>> index 0bfcf7e..f7d2c8f 100644
>> --- a/arch/x86/include/asm/processor.h
>> +++ b/arch/x86/include/asm/processor.h
>> @@ -403,7 +403,17 @@ extern unsigned long kernel_eflags;
>> extern asmlinkage void ignore_sysret(void);
>> #else /* X86_64 */
>> #ifdef CONFIG_CC_STACKPROTECTOR
>> -DECLARE_PER_CPU(unsigned long, stack_canary);
>> +/*
>> + * Make sure stack canary segment base is cached-aligned:
>> + * "For Intel Atom processors, avoid non zero segment base address
>> + * that is not aligned to cache line boundary at all cost."
>> + * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
>> + */
>> +struct stack_canary {
>> + char __pad[20]; /* canary at %gs:20 */
>> + unsigned long canary;
>> +};
>> +DECLARE_PER_CPU(struct stack_canary, stack_canary) ____cacheline_aligned;
>>
> DECLARE_PER_CPU_SHARED_ALIGNED()
>
> Or else, we'll have many holes in percpu section, because of linker encapsulation
>

That's only cache aligned when SMP is enabled, to avoid false cacheline
sharing. In this case we need it unconditionally cache-aligned.

J