Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned

Tejun Heo
2009-09-04T16:10:06Z

Jeremy Fitzhardinge wrote:
> On 09/03/09 22:06, Tejun Heo wrote:
>>>> Heh... here's a naive and hopeful plan. How about we beg gcc
>>>> developers to allow different segment register and offset in newer gcc
>>>> versions and then use the same one when building with the new gcc?
>>>> This should solve the i386 problem too. It would be the best as we
>>>> get to keep the separate segment register from the userland. Too
>>>> hopeful?
>>>>
>>> I think it's possible to set the register in more recent gcc. Doing the
>>> sane thing and having a symbol for an offset is probably worse.
>>>
>> I was thinking about altering the build process so that we can use sed
>> to substitute %gs:40 with %fs:40 while compiling. If it's already
>> possible to override the register in more recent gcc, no need to go
>> into that horror.
>>
>
> Ideally we'd like to get rid of the constant offset too. If we could
> change it to %[fg]s:__gcc_stack_canary_offset on both 32-bit and 64-bit,
> it would give us a lot more flexibility. __gcc_stack_canary_offset
> could be weakly defined to 20/40 for backwards compatibility, but we
> could override it to point to a normal percpu variable.

Yeap, being able to do that will also allow using single segment
register on i386 too. But given that the only overhead we're talking
here is a few more cycles when entering and leving the kernel, I don't
think we need to do anything drastic to optimize this. I think
converting when gcc provides the feature should be enough.

Thanks.

--
tejun