Re: [PATCH 03/10] KVM: SVM: Fix schedule-while-atomic on nested exception handling

Joerg Roedel
2010-02-18T16:24:37Z

On Thu, Feb 18, 2010 at 03:52:20PM +0200, Avi Kivity wrote:
> On 02/18/2010 01:38 PM, Joerg Roedel wrote:
> >Move the actual vmexit routine out of code that runs with
> >irqs and preemption disabled.
> >
> >Cc: stable@kernel.org
> >Signed-off-by: Joerg Roedel<joerg.roedel@amd.com>
> >---
> > arch/x86/kvm/svm.c | 20 +++++++++++++++++---
> > 1 files changed, 17 insertions(+), 3 deletions(-)
> >
> >diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> >index 7c96b8b..25d26ec 100644
> >--- a/arch/x86/kvm/svm.c
> >+++ b/arch/x86/kvm/svm.c
> >@@ -128,6 +128,7 @@ static void svm_flush_tlb(struct kvm_vcpu *vcpu);
> > static void svm_complete_interrupts(struct vcpu_svm *svm);
> >
> > static int nested_svm_exit_handled(struct vcpu_svm *svm);
> >+static int nested_svm_exit_handled_atomic(struct vcpu_svm *svm);
> > static int nested_svm_vmexit(struct vcpu_svm *svm);
> > static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
> > bool has_error_code, u32 error_code);
> >@@ -1386,7 +1387,7 @@ static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
> > svm->vmcb->control.exit_info_1 = error_code;
> > svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
> >
> >- return nested_svm_exit_handled(svm);
> >+ return nested_svm_exit_handled_atomic(svm);
> > }
>
> What do you say to
>
>
> if (nested_svm_intercepts(svm))
> svm->nested.exit_required = true;
>
> here, and recoding nested_svm_exit_handled() to call
> nested_svm_intercepts()? I think it improves readability a little
> by avoiding a function that changes behaviour according to how it is
> called.

Thats a good idea, will change that. It improves readability.

> Long term, we may want to split out the big switch into the
> individual handlers, to avoid decoding the exit reason twice.

I don't think thats a good idea. The nested exit handling is at the
beginning of svm_handle_exit to hide the nested vcpu state from the kvm
logic which may not be aware of nesting at all. My rationale is that the
host hypervisor don't see any exits that needs to be reinjected to the
l1 hypervisor.

Joerg