Tilera multi core: power consumption, design, performance (comments please)

Tilera multi core: power consumption, design, performance (comments please)

[Reza Roboubi]

LKML is very quite about the Tilera multi core chip.  I'm wondering why 
that is?

I know the debate about RISC/VLIW vs. non-RISC/OoO.  However, what do 
people think about the overall performance of Tilera given it's low 
power consumption (~55 watts) as far as it's intended (parallelizable) 
applications are concerned?

I looked at the Tilera patent number 7,636,835.  It looks like a decent 
directory based cache coherency solution that is very scalable.

So, please give comments if you can.
Why is the chip not discussed at LKML?  Is it cost or lack of documentation?

Thanks.

Reza.