in x86 architecture ,why the function atomic_sub_and_test() does not disable the interrupt?

in x86 architecture ,why the function atomic_sub_and_test() does not disable the interrupt?

[杨硕]

static inline int atomic_sub_and_test(int i, atomic_t *v)
{
	unsigned char c;

	asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
		     : "+m" (v->counter), "=qm" (c)
		     : "ir" (i) : "memory");
	return c;
}

TIA:)

Re: in x86 architecture ,why the function atomic_sub_and_test() does not disable the interrupt?

[Roland Dreier]

 > static inline int atomic_sub_and_test(int i, atomic_t *v)
 > {
 > 	unsigned char c;
 > 
 > 	asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
 > 		     : "+m" (v->counter), "=qm" (c)
 > 		     : "ir" (i) : "memory");
 > 	return c;
 > }

Why would disabling interrupts be necessary?  The LOCK_PREFIX makes the
subl atomic, and the sete just operates using the flag set by subl, so
it doesn't matter if any interrupts occur or not (since returning from
an interrupt must obviously restore flags).
-- 
Roland Dreier <rolandd@cisco.com> || For corporate legal information go to:
http://www.cisco.com/web/about/doing_business/legal/cri/index.html

Re: in x86 architecture ,why the function atomic_sub_and_test() does not disable the interrupt?

[H. Peter Anvin]

On 04/05/2010 11:07 PM, Roland Dreier wrote:
>  > static inline int atomic_sub_and_test(int i, atomic_t *v)
>  > {
>  > 	unsigned char c;
>  > 
>  > 	asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
>  > 		     : "+m" (v->counter), "=qm" (c)
>  > 		     : "ir" (i) : "memory");
>  > 	return c;
>  > }
> 
> Why would disabling interrupts be necessary?  The LOCK_PREFIX makes the
> subl atomic, and the sete just operates using the flag set by subl, so
> it doesn't matter if any interrupts occur or not (since returning from
> an interrupt must obviously restore flags).

Even without the LOCK prefix, subl would be atomic against local
interrupts.  The LOCK prefix is only necessary to make it atomic against
other processors.

	-hpa