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Date: Wed, 12 May 2010 09:55:48 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
CC: Ananth N Mavinakayanahalli <ananth@in.ibm.com>,
       Peter Zijlstra <peterz@infradead.org>,
       Srikar Dronamraju <srikar@linux.vnet.ibm.com>,
       Ingo Molnar <mingo@elte.hu>, Masami Hiramatsu <mhiramat@redhat.com>,
       Mel Gorman <mel@csn.ul.ie>, Randy Dunlap <rdunlap@xenotime.net>,
       Linus Torvalds <torvalds@linux-foundation.org>,
       Roland McGrath <roland@redhat.com>, Oleg Nesterov <oleg@redhat.com>,
       Mark Wielaard <mjw@redhat.com>, LKML <linux-kernel@vger.kernel.org>,
       Jim Keniston <jkenisto@linux.vnet.ibm.com>,
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       "Frank Ch. Eigler" <fche@redhat.com>,
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       Rik van Riel <riel@redhat.com>,
       "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Subject: Re: [PATCH v3 0/10] Uprobes v3
References: <20100506180139.28877.81699.sendpatchset@localhost6.localdomain6> <1273611585.1810.132.camel@laptop> <20100512102518.GA30767@linux.vnet.ibm.com> <1273666385.1626.96.camel@laptop> <20100512132708.GC13606@in.ibm.com> <1273671560.1626.114.camel@laptop> <20100512140433.GD13606@in.ibm.com> <20100512144629.GA16343@Krystal>
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On 05/12/2010 07:46 AM, Mathieu Desnoyers wrote:
> 
> Now the tricky case is the sequence: instruction A -> int3 -> instruction B,
> because a core can only see "instruction A -> instruction B" without any
> core synchronization whatsoever, and may not see the int3. That's where the
> djprobes logic (with IPIs to all cores) comes into play. But as long as we stick
> to "insn A -> int3 -> insn A", things can be done very simply.
> 
> By the way, kprobes rely on the assumption that it is OK to put a breakpoint
> atomically and to put back the original instruction afterward.
> 

Keep in mind the following corner case, though:

insnA -> int3@A -> insnA
insnB -> int3@B -> insnB

It is now possible for the core to hit int3@A, without the int3@B being
there.  The int3 handler *has* to be able to handle any of the int3's
put in place, quite possibly out of order, until a core serialization is
performed.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.