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From: Corey Ashford <cjashfor@linux.vnet.ibm.com>
To: Robert Richter <robert.richter@amd.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
	Ingo Molnar <mingo@elte.hu>,
	Stephane Eranian <eranian@google.com>,
	LKML <linux-kernel@vger.kernel.org>,
	Lin Ming <ming.m.lin@intel.com>
Subject: Re: [PATCH 1/7] perf: introduce raw_type attribute to specify the type of a raw sample
Date: Wed, 19 May 2010 15:02:40 -0700	[thread overview]
Message-ID: <4BF46000.20203@linux.vnet.ibm.com> (raw)
In-Reply-To: <1274304024-6551-2-git-send-email-robert.richter@amd.com>

Hi Robert,

On 5/19/2010 2:20 PM, Robert Richter wrote:
> This patch introduces a method to specify the type of a raw sample.
> This can be used to setup hardware events other than generic
> performance counters by passing special config data to the pmu. The
> config data can be interpreted different from generic events and thus
> can be used for other purposes.
> 
> The raw_type attribute is an extension of the ABI. It reuses the
> unused bp_type space for this. Generic performance counters can be
> setup by setting the raw_type attribute to null. Thus special raw
> events must have a type other than null.
> 
> Raw types can be defined as needed for cpu models or architectures.
> To keep backward compatibility all architectures must return an error
> for an event with a raw_type other than null that is not supported.
> 
> E.g., raw_type can be used to setup IBS on an AMD cpu. IBS is not
> common to pmu features from other vendors or architectures. The pmu
> must be setup with a special config value. Sample data is returned in
> a certain format back to the userland. An IBS event is created by
> setting a raw event and encoding the IBS type in raw_type. The pmu
> handles this raw event then and passes raw sample data back.
> 
> Raw type could be architecure specific, e.g. for x86:
> 
> enum perf_raw_type {
>         PERF_RAW_PERFCTR                        = 0,
>         PERF_RAW_IBS_FETCH                      = 1,
>         PERF_RAW_IBS_OP                         = 2,
> 
>         PERF_RAW_MAX,
> };
> 
> Null is the architecture's default, meaning for x86 a perfctr.
> 
> Maybe the raw type definition could also be part of the ABI with one
> definition for all architectures.
> 
> To use raw events with perf, the raw event syntax could be suffixed by
> the type (as for breakpoints):
> 
>    -e rNNN[:TYPE]
> 
> Example:
> 
>  perf record -e r186A:1          # ... meaning IBS fetch, cycle count 100000
>  perf record -e r0:1 -c 100000   # ... the same
> 
> Or with named types:
> 
>  perf record -e r186A:IBS_FETCH ...
>  perf record -e r0:IBS_FETCH -c 100000 ...

Should this raw value have been 186A0 instead of 186A?

Where is the named type translation coming from?  Is this something that needs to be hard-coded into perf?

Have you looked at Lin Ming's patch series?  I think it offers another way to support IBS and other arch-specific and off-chip PMUs in a more general way, though it's not quite fully-baked yet.

- Corey


  reply	other threads:[~2010-05-19 22:02 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-05-19 21:20 [PATCH 0/7] perf: implement AMD IBS (v2) Robert Richter
2010-05-19 21:20 ` [PATCH 1/7] perf: introduce raw_type attribute to specify the type of a raw sample Robert Richter
2010-05-19 22:02   ` Corey Ashford [this message]
2010-05-20  6:51     ` Ingo Molnar
2010-05-20 23:06       ` Robert Richter
2010-05-20 22:46     ` Robert Richter
2010-05-20  8:10   ` Stephane Eranian
2010-05-20  9:23     ` Peter Zijlstra
2010-05-20  9:42       ` Stephane Eranian
2010-05-20 10:37         ` Peter Zijlstra
2010-05-20 12:13           ` Stephane Eranian
2010-05-20 15:22             ` Robert Richter
2012-11-23 12:00               ` Robert Richter
2010-05-20 14:08           ` Robert Richter
2010-05-20 16:55             ` Ingo Molnar
2010-05-20 17:07               ` Robert Richter
2010-05-20 17:16                 ` Peter Zijlstra
2010-05-20 13:58       ` Robert Richter
2010-05-20 14:14         ` Stephane Eranian
2010-05-20 14:30           ` Stephane Eranian
2010-05-20 15:48           ` Robert Richter
2010-05-19 21:20 ` [PATCH 2/7] perf, x86: introduce bit range for special pmu events Robert Richter
2010-05-19 21:20 ` [PATCH 3/7] perf, x86: modify some code to allow the introduction of ibs events Robert Richter
2010-05-19 21:20 ` [PATCH 4/7] perf, x86: implement IBS feature detection Robert Richter
2010-05-19 21:20 ` [PATCH 5/7] perf, x86: setup NMI handler for IBS Robert Richter
2010-05-19 21:20 ` [PATCH 6/7] perf, x86: implement AMD IBS event configuration Robert Richter
2010-05-19 21:20 ` [PATCH 7/7] perf, x86: implement the ibs interrupt handler Robert Richter

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