From: Andi Kleen <ak@linux.intel.com>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>,
linux-kernel@vger.kernel.org, fweisbec@gmail.com,
a.p.zijlstra@chello.nl, mingo@elte.hu, acme@redhat.com
Subject: Re: [PATCH 1/3] perf-events: Add support for supplementary event registers
Date: Thu, 11 Nov 2010 19:42:03 +0100 [thread overview]
Message-ID: <4CDC38FB.20303@linux.intel.com> (raw)
In-Reply-To: <AANLkTi=3xQd-anvwXryXASr1+Th1HSjTn8j-ZcRZko3b@mail.gmail.com>
On 11/11/2010 7:06 PM, Stephane Eranian wrote:
Thanks for the review.
> One thing I noticed in your patch is that you don't special
> case the configuration where HT is off. In that case, the
> sharing problem goes away. I think you could override
> either way during init.
The allocator should handle that transparently. With HT off the resource is
always free. Or do you see any concrete problems with the current code path?
> Some more tidbits:
> - OFFCORE_RESPONSE_0 is 0x01b7
> - OFFCORE_RESPONSE_1 is 0x01bb
>
> The umask is not zero but 1. Dont' know if you get
> something meaningful is you pass a umask of zero.
Hmm I seem to get events that look meaningful with 0. But you're right 1
is better. I used that in manual tests, but it wasn't in the cache number
mappings. I'll fix that for the next version.
-Andi
next prev parent reply other threads:[~2010-11-11 18:42 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-11 16:15 [PATCH 1/3] perf-events: Add support for supplementary event registers Andi Kleen
2010-11-11 16:15 ` [PATCH 2/3] perf: Add support for extra parameters for raw events Andi Kleen
2010-11-11 17:54 ` Corey Ashford
2010-11-11 18:39 ` Andi Kleen
2010-11-11 19:38 ` Corey Ashford
2010-11-11 19:49 ` Andi Kleen
2010-11-11 19:59 ` Peter Zijlstra
2010-11-11 20:12 ` Andi Kleen
2010-11-11 20:37 ` Peter Zijlstra
2010-11-12 10:27 ` Andi Kleen
2010-11-12 10:49 ` Stephane Eranian
2010-11-12 11:36 ` Peter Zijlstra
2010-11-12 13:00 ` Stephane Eranian
2010-11-12 13:21 ` Peter Zijlstra
2010-11-12 14:03 ` Stephane Eranian
2010-11-12 13:30 ` Frederic Weisbecker
2010-11-12 15:00 ` Stephane Eranian
2010-11-12 10:41 ` Stephane Eranian
2010-11-12 10:48 ` Peter Zijlstra
2010-11-12 10:39 ` Stephane Eranian
2010-11-12 10:48 ` Andi Kleen
2010-11-12 10:52 ` Stephane Eranian
2010-11-12 10:56 ` Stephane Eranian
2010-11-11 16:15 ` [PATCH 3/3] perf-events: Fix LLC-* events on Intel Nehalem/Westmere Andi Kleen
2010-11-11 17:35 ` [PATCH/FIX] perf-events: Put the per cpu state for intel_pmu too Andi Kleen
2010-11-11 17:54 ` Stephane Eranian
2010-11-11 18:44 ` Andi Kleen
2010-11-11 21:29 ` Stephane Eranian
2010-11-11 18:06 ` [PATCH 1/3] perf-events: Add support for supplementary event registers Stephane Eranian
2010-11-11 18:42 ` Andi Kleen [this message]
2010-11-11 19:09 ` Peter Zijlstra
2010-11-11 19:25 ` Andi Kleen
2010-11-11 19:36 ` Peter Zijlstra
2010-11-11 19:45 ` Andi Kleen
2010-11-11 19:49 ` Peter Zijlstra
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