From: Boris Ostrovsky <boris.ostrovsky@amd.com>
To: Hans Rosenfeld <hans.rosenfeld@amd.com>,
Chuck Ebbert <cebbert@redhat.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Petkov, Borislav" <Borislav.Petkov@amd.com>
Subject: Re: [PATCH] cpu, AMD: Fix another bug in the new errata checking code
Date: Fri, 13 May 2011 09:03:59 -0400 [thread overview]
Message-ID: <4DCD2C3F.9070905@amd.com> (raw)
In-Reply-To: <20110513102154.GB9270@escobedo.osrc.amd.com>
On 05/13/2011 06:21 AM, Hans Rosenfeld wrote:
> On Thu, May 12, 2011 at 07:59:38PM -0400, Chuck Ebbert wrote:
> The revision guide states that family 0x10 model 6 stepping 2 has E400.
> So I would expect that OSVW length is>= 2 and that OSVW status has bit
> 1 set, or that OSVW length is< 2. This indicates that the workaround is
> necessary, without any need to check the family-model-stepping ranges.
>
> It would also be correct if the BIOS disabled C1E and cleared the
> corresponding OSVW status bit. Anything else would probably be a very
> nasty BIOS bug.
>
> Could you send me the contents of MSRs 0xc0010140, 0xc0010141 and
> 0xc0010055?
Knowing whether any C state above C1 is declared could be useful too.
-boris
next prev parent reply other threads:[~2011-05-13 13:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-12 23:59 [PATCH] cpu, AMD: Fix another bug in the new errata checking code Chuck Ebbert
2011-05-13 10:21 ` Hans Rosenfeld
2011-05-13 13:03 ` Boris Ostrovsky [this message]
2011-05-13 14:59 ` Chuck Ebbert
2011-05-13 15:19 ` Hans Rosenfeld
2011-05-16 12:43 ` Chuck Ebbert
2011-05-16 13:38 ` Boris Ostrovsky
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