[PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[Naga Chumbalkar]

If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.

The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2 
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).

Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8..f7b0c7a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1429,7 +1429,7 @@ void enable_x2apic(void)
 	rdmsr(MSR_IA32_APICBASE, msr, msr2);
 	if (!(msr & X2APIC_ENABLE)) {
 		printk_once(KERN_INFO "Enabling x2apic\n");
-		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
 	}
 }
 #endif /* CONFIG_X86_X2APIC */

Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[Cyrill Gorcunov]

On Tue, Jul 12, 2011 at 05:59:07AM +0000, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
> 
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2 
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
> 
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
> 

Looks like a good idea for me. I've reviewed some additional specs
and even some updates, nothing interesting found.

Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>

Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[Suresh Siddha]

On Mon, 2011-07-11 at 22:59 -0700, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
> 
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2 
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
> 
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
> 
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index b9338b8..f7b0c7a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1429,7 +1429,7 @@ void enable_x2apic(void)
>  	rdmsr(MSR_IA32_APICBASE, msr, msr2);
>  	if (!(msr & X2APIC_ENABLE)) {
>  		printk_once(KERN_INFO "Enabling x2apic\n");
> -		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
> +		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
>  	}
>  }
>  #endif /* CONFIG_X86_X2APIC */

yeah, I don't think it was intentional.

Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>

Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[H. Peter Anvin]

On 07/12/2011 10:29 AM, Suresh Siddha wrote:
> 
> yeah, I don't think it was intentional.
> 
> Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
> 

This isn't 3.0 material, though (no manifest error), correct?

	-hpa

Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[Suresh Siddha]

On Tue, 2011-07-12 at 11:21 -0700, H. Peter Anvin wrote:
> On 07/12/2011 10:29 AM, Suresh Siddha wrote:
> > 
> > yeah, I don't think it was intentional.
> > 
> > Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
> > 
> 
> This isn't 3.0 material, though (no manifest error), correct?

Yep. Right Naga?

RE: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[Chumbalkar, Nagananda]

>-----Original Message-----
>From: Suresh Siddha [mailto:suresh.b.siddha@intel.com]
>Sent: Tuesday, July 12, 2011 1:36 PM
>To: H. Peter Anvin
>Cc: Chumbalkar, Nagananda; x86@kernel.org; linux-kernel@vger.kernel.org;
>mingo@elte.hu; tglx@linutronix.de
>Subject: Re: [PATCH] x86, x2apic: Preserve high 32-bits of
>IA32_APIC_BASE MSR
>
>On Tue, 2011-07-12 at 11:21 -0700, H. Peter Anvin wrote:
>> On 07/12/2011 10:29 AM, Suresh Siddha wrote:
>> >
>> > yeah, I don't think it was intentional.
>> >
>> > Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
>> >
>>
>> This isn't 3.0 material, though (no manifest error), correct?
>
>Yep. Right Naga?

That's correct. No manifest errors. This patch can wait.

- naga -

[tip:x86/apic] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

[tip-bot for Naga Chumbalkar]

Commit-ID:  25970852280c9d5fb2de899769880d3e97332baa
Gitweb:     http://git.kernel.org/tip/25970852280c9d5fb2de899769880d3e97332baa
Author:     Naga Chumbalkar <nagananda.chumbalkar@hp.com>
AuthorDate: Tue, 12 Jul 2011 05:59:07 +0000
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 12 Jul 2011 14:33:49 -0700

x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.

The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).

Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Link: http://lkml.kernel.org/r/20110712055831.2498.78521.sendpatchset@nchumbalkar.americas.cpqcorp.net
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/kernel/apic/apic.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8..f7b0c7a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1429,7 +1429,7 @@ void enable_x2apic(void)
 	rdmsr(MSR_IA32_APICBASE, msr, msr2);
 	if (!(msr & X2APIC_ENABLE)) {
 		printk_once(KERN_INFO "Enabling x2apic\n");
-		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
 	}
 }
 #endif /* CONFIG_X86_X2APIC */