From: "H. Peter Anvin" <hpa@zytor.com>
To: Christoph Lameter <cl@linux.com>
Cc: "H. Peter Anvin" <hpa@linux.intel.com>,
Ingo Molnar <mingo@elte.hu>,
linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>
Subject: Re: [x86] Fix prefetch instruction
Date: Fri, 05 Aug 2011 16:53:33 -0700 [thread overview]
Message-ID: <4E3C827D.9040303@zytor.com> (raw)
In-Reply-To: <alpine.DEB.2.00.1108051831090.13276@router.home>
On 08/05/2011 04:32 PM, Christoph Lameter wrote:
>>
>> Right. However, Linus has brought up the hypothesis that prefetch might
>> actually be a net loss on x86, because current x86 processors are
>> generally doing a good job with prefetching in hardware. Directed
>> prefetches can thus be a net minus.
>
> This kinid of prefetch is a minus because the cache is evicted early. It
> was prefetched with a special hint so its likely very important. That does
> not seem to be very consistent and may cause regressions. Changing it to a
> full prefetch would make the important cacheline stay longer in the cache.
>
The argument applies not just to NTA prefetches, though. There is a
pipeline cost to performing the software prefetch action, it can cause
evictions if the data is not used, and it can increase TLB pressure.
As such, it would be very interesting to know if prefetch0 or nothing is
the better; agree we shouldn't nta here.
-hpa
prev parent reply other threads:[~2011-08-05 23:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-05 16:18 [x86] Fix prefetch instruction Christoph Lameter
2011-08-05 20:13 ` H. Peter Anvin
2011-08-05 21:10 ` Christoph Lameter
2011-08-05 21:22 ` H. Peter Anvin
2011-08-05 23:32 ` Christoph Lameter
2011-08-05 23:53 ` H. Peter Anvin [this message]
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