* [PATCH V2 1/4] MIPS: Add CPU support for Loongson1B
@ 2011-10-21 10:28 keguang.zhang
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: keguang.zhang @ 2011-10-21 10:28 UTC (permalink / raw)
To: linux-mips, linux-kernel; +Cc: ralf, wuzhangjin, r0bertz, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch adds CPU support for Loongson1B.
Loongson 1B is a 32-bit SoC designed by Institute of
Computing Technology (ICT), Chinese Academy of Sciences (CAS),
which implements the MIPS32 release 2 instruction set.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
arch/mips/include/asm/module.h | 2 ++
arch/mips/kernel/cpu-probe.c | 15 +++++++++++++++
arch/mips/kernel/perf_event_mipsxx.c | 6 ++++++
arch/mips/kernel/traps.c | 1 +
arch/mips/oprofile/common.c | 1 +
arch/mips/oprofile/op_model_mipsxx.c | 4 ++++
7 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 5f95a4b..975f372 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -191,6 +191,7 @@
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
+#define PRID_REV_LOONGSON1B 0x0020
/*
* Older processors used to encode processor version and revision in two
@@ -253,7 +254,7 @@ enum cpu_type_enum {
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
- CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
+ CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1,
/*
* MIPS64 class processors
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02..b53d642 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "SB1 "
#elif defined CONFIG_CPU_LOONGSON2
#define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_LOONGSON1
+#define MODULE_PROC_FAMILY "LOONGSON1 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 664bc13..98d4235 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -37,6 +37,8 @@
void (*cpu_wait)(void);
EXPORT_SYMBOL(cpu_wait);
+static void __cpuinit decode_configs(struct cpuinfo_mips *c);
+
static void r3081_wait(void)
{
unsigned long cfg = read_c0_conf();
@@ -191,6 +193,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_XLR:
+ case CPU_LOONGSON1:
cpu_wait = r4k_wait;
break;
@@ -636,6 +639,18 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
MIPS_CPU_32FPR;
c->tlbsize = 64;
break;
+ case PRID_IMP_LOONGSON1:
+ decode_configs(c);
+
+ c->cputype = CPU_LOONGSON1;
+
+ switch (c->processor_id & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON1B:
+ __cpu_name[cpu] = "Loongson 1B";
+ break;
+ }
+
+ break;
}
}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index e5ad09a..e316b0e 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1062,6 +1062,12 @@ init_hw_perf_events(void)
mipsxxcore_pmu.irq = irq;
mipspmu = &mipsxxcore_pmu;
break;
+ case CPU_LOONGSON1:
+ mipsxxcore_pmu.name = "mips/loongson1";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
default:
pr_cont("Either hardware does not support performance "
"counters, or not yet implemented.\n");
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 01eff7e..cd55823 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1241,6 +1241,7 @@ static inline void parity_protection_init(void)
break;
case CPU_5KC:
+ case CPU_LOONGSON1:
write_c0_ecc(0x80000000);
back_to_back_c0_hazard();
/* Set the PE bit (bit 31) in the c0_errctl register. */
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index d1f2d4c..99216f0 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -89,6 +89,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case CPU_R10000:
case CPU_R12000:
case CPU_R14000:
+ case CPU_LOONGSON1:
lmodel = &op_model_mipsxx_ops;
break;
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..03be670 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -365,6 +365,10 @@ static int __init mipsxx_init(void)
op_model_mipsxx_ops.cpu_type = "mips/sb1";
break;
+ case CPU_LOONGSON1:
+ op_model_mipsxx_ops.cpu_type = "mips/loongson1";
+ break;
+
default:
printk(KERN_ERR "Profiling unsupported for this CPU\n");
--
1.7.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-21 10:28 [PATCH V2 1/4] MIPS: Add CPU support for Loongson1B keguang.zhang
@ 2011-10-21 10:28 ` keguang.zhang
2011-10-21 17:33 ` Wu Zhangjin
2011-11-16 14:10 ` Ralf Baechle
2011-10-21 10:28 ` [PATCH V2 3/4] MIPS: Add Makefile and Kconfig " keguang.zhang
2011-10-21 10:28 ` [PATCH V2 4/4] MIPS: Add defconfig " keguang.zhang
2 siblings, 2 replies; 19+ messages in thread
From: keguang.zhang @ 2011-10-21 10:28 UTC (permalink / raw)
To: linux-mips, linux-kernel; +Cc: ralf, wuzhangjin, r0bertz, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch adds basic platform support for Loongson1B
including serial port, ethernet, and interrupt handler.
Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
arch/mips/include/asm/mach-loongson1/irq.h | 68 +++++++++
arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++
arch/mips/include/asm/mach-loongson1/platform.h | 21 +++
arch/mips/include/asm/mach-loongson1/prom.h | 24 +++
arch/mips/include/asm/mach-loongson1/regs-clk.h | 32 ++++
arch/mips/include/asm/mach-loongson1/regs-intc.h | 25 ++++
arch/mips/include/asm/mach-loongson1/regs-wdt.h | 21 +++
arch/mips/include/asm/mach-loongson1/war.h | 25 ++++
arch/mips/loongson1/common/clock.c | 165 ++++++++++++++++++++++
arch/mips/loongson1/common/irq.c | 136 ++++++++++++++++++
arch/mips/loongson1/common/platform.c | 94 ++++++++++++
arch/mips/loongson1/common/prom.c | 88 ++++++++++++
arch/mips/loongson1/common/reset.c | 46 ++++++
arch/mips/loongson1/common/setup.c | 29 ++++
arch/mips/loongson1/ls1b/board.c | 31 ++++
drivers/net/stmmac/descs.h | 68 +++++++++
drivers/net/stmmac/enh_desc.c | 16 ++
17 files changed, 933 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
create mode 100644 arch/mips/include/asm/mach-loongson1/regs-intc.h
create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
create mode 100644 arch/mips/loongson1/common/clock.c
create mode 100644 arch/mips/loongson1/common/irq.c
create mode 100644 arch/mips/loongson1/common/platform.c
create mode 100644 arch/mips/loongson1/common/prom.c
create mode 100644 arch/mips/loongson1/common/reset.c
create mode 100644 arch/mips/loongson1/common/setup.c
create mode 100644 arch/mips/loongson1/ls1b/board.c
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 0000000..6373f53
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE 0
+#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
+#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
+#define INT0_IRQ MIPS_CPU_IRQ(2)
+#define INT1_IRQ MIPS_CPU_IRQ(3)
+#define INT2_IRQ MIPS_CPU_IRQ(4)
+#define INT3_IRQ MIPS_CPU_IRQ(5)
+#define INT4_IRQ MIPS_CPU_IRQ(6)
+#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE 8
+#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
+
+#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
+#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
+#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
+#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
+#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
+#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
+#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
+
+#define LS1X_OHCI_IRQ LS1X_IRQ(1, 0)
+#define LS1X_EHCI_IRQ LS1X_IRQ(1, 1)
+#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
+#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
+
+#define NR_IRQS LS1X_GMAC1_IRQ
+
+#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 0000000..2946046
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Register mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
+#define __ASM_MACH_LOONGSON1_LOONGSON1_H
+
+#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
+
+/* Loongson1 Register Bases */
+#define LS1X_INTC_BASE 0x1fd01040
+#define LS1X_USB_BASE 0x1fe00000
+#define LS1X_GMAC0_BASE 0x1fe10000
+#define LS1X_GMAC1_BASE 0x1fe20000
+
+#define LS1X_UART0_BASE 0x1fe40000
+#define LS1X_UART1_BASE 0x1fe44000
+#define LS1X_UART2_BASE 0x1fe48000
+#define LS1X_UART3_BASE 0x1fe4c000
+#define LS1X_CAN0_BASE 0x1fe50000
+#define LS1X_CAN1_BASE 0x1fe54000
+#define LS1X_I2C0_BASE 0x1fe58000
+#define LS1X_I2C1_BASE 0x1fe68000
+#define LS1X_I2C2_BASE 0x1fe70000
+#define LS1X_PWM_BASE 0x1fe5c000
+#define LS1X_WDT_BASE 0x1fe5c060
+#define LS1X_RTC_BASE 0x1fe64000
+#define LS1X_AC97_BASE 0x1fe74000
+#define LS1X_NAND_BASE 0x1fe78000
+#define LS1X_CLK_BASE 0x1fe78030
+
+#include <regs-clk.h>
+#include <regs-intc.h>
+#include <regs-wdt.h>
+
+#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 0000000..1e4b313
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
+#define __ASM_MACH_LOONGSON1_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device ls1x_uart_device;
+extern struct platform_device ls1x_eth0_device;
+
+void ls1x_serial_setup(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 0000000..b871dc4
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_PROM_H
+#define __ASM_MACH_LOONGSON1_PROM_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+/* environment arguments from bootloader */
+extern unsigned long memsize, highmemsize;
+
+/* loongson-specific command line, env and memory initialization */
+extern char *prom_getenv(char *name);
+extern void __init prom_init_cmdline(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 0000000..4f488c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson1 Clock Register Definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
+#define __ASM_MACH_LOONGSON1_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) (ioremap(LS1X_CLK_BASE + (x), 4))
+
+#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
+
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN (0x1 << 31)
+#define DIV_DC (0x1f << 26)
+#define DIV_CPU_EN (0x1 << 25)
+#define DIV_CPU (0x1f << 20)
+#define DIV_DDR_EN (0x1 << 19)
+#define DIV_DDR (0x1f << 14)
+
+#define DIV_DC_SHIFT 26
+#define DIV_CPU_SHIFT 20
+#define DIV_DDR_SHIFT 14
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-intc.h b/arch/mips/include/asm/mach-loongson1/regs-intc.h
new file mode 100644
index 0000000..6d5db23
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-intc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson1 Interrupt register definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_INTC_H
+#define __ASM_MACH_LOONGSON1_REGS_INTC_H
+
+#define LS1X_INTC_REG(n, x) \
+ (ioremap(LS1X_INTC_BASE + (n * 0x18) + (x), 4))
+
+#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
+#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
+#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
+#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
+#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
+#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_INTC_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 0000000..875ce67
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson1 Watchdog register definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
+#define __ASM_MACH_LOONGSON1_REGS_WDT_H
+
+#define LS1X_WDT_REG(x) (ioremap(LS1X_WDT_BASE + (x), 4))
+
+#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
+#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
+#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 0000000..e3680a8
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_LOONGSON1_WAR_H
+#define __ASM_MACH_LOONGSON1_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
new file mode 100644
index 0000000..2d98fb0
--- /dev/null
+++ b/arch/mips/loongson1/common/clock.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/clock.h>
+#include <asm/time.h>
+
+#include <loongson1.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+ struct clk *c;
+ struct clk *ret = NULL;
+
+ mutex_lock(&clocks_mutex);
+ list_for_each_entry(c, &clocks, node) {
+ if (!strcmp(c->name, name)) {
+ ret = c;
+ break;
+ }
+ }
+ mutex_unlock(&clocks_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_get);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+static void pll_clk_init(struct clk *clk)
+{
+ u32 pll;
+
+ pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+ clk->rate = (12 + (pll & 0x3f)) * 33 / 2
+ + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
+ clk->rate *= 1000000;
+}
+
+static void cpu_clk_init(struct clk *clk)
+{
+ u32 pll, ctrl;
+
+ pll = clk_get_rate(clk->parent);
+ ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
+ clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
+}
+
+static void ddr_clk_init(struct clk *clk)
+{
+ u32 pll, ctrl;
+
+ pll = clk_get_rate(clk->parent);
+ ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
+ clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
+}
+
+static void dc_clk_init(struct clk *clk)
+{
+ u32 pll, ctrl;
+
+ pll = clk_get_rate(clk->parent);
+ ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
+ clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
+}
+
+static struct clk_ops pll_clk_ops = {
+ .init = pll_clk_init,
+};
+
+static struct clk_ops cpu_clk_ops = {
+ .init = cpu_clk_init,
+};
+
+static struct clk_ops ddr_clk_ops = {
+ .init = ddr_clk_init,
+};
+
+static struct clk_ops dc_clk_ops = {
+ .init = dc_clk_init,
+};
+
+static struct clk pll_clk = {
+ .name = "pll",
+ .ops = &pll_clk_ops,
+};
+
+static struct clk cpu_clk = {
+ .name = "cpu",
+ .parent = &pll_clk,
+ .ops = &cpu_clk_ops,
+};
+
+static struct clk ddr_clk = {
+ .name = "ddr",
+ .parent = &pll_clk,
+ .ops = &ddr_clk_ops,
+};
+
+static struct clk dc_clk = {
+ .name = "dc",
+ .parent = &pll_clk,
+ .ops = &dc_clk_ops,
+};
+
+int clk_register(struct clk *clk)
+{
+ mutex_lock(&clocks_mutex);
+ list_add(&clk->node, &clocks);
+ if (clk->ops->init)
+ clk->ops->init(clk);
+ mutex_unlock(&clocks_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+static struct clk *ls1x_clks[] = {
+ &pll_clk,
+ &cpu_clk,
+ &ddr_clk,
+ &dc_clk,
+};
+
+int __init ls1x_clock_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++)
+ clk_register(ls1x_clks[i]);
+
+ return 0;
+}
+
+void __init plat_time_init(void)
+{
+ struct clk *clk;
+
+ /* Initialize LS1X clocks */
+ ls1x_clock_init();
+
+ /* setup mips r4k timer */
+ clk = clk_get(NULL, "cpu");
+ if (IS_ERR(clk))
+ panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+
+ mips_hpt_frequency = clk_get_rate(clk) / 2;
+}
diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c
new file mode 100644
index 0000000..a33bf85
--- /dev/null
+++ b/arch/mips/loongson1/common/irq.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <loongson1.h>
+#include <irq.h>
+
+static void ls1x_irq_ack(struct irq_data *d)
+{
+ unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+ unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+ __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+ | (1 << bit), LS1X_INTC_INTCLR(n));
+}
+
+static void ls1x_irq_mask(struct irq_data *d)
+{
+ unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+ unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+ __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ & ~(1 << bit), LS1X_INTC_INTIEN(n));
+}
+
+static void ls1x_irq_mask_ack(struct irq_data *d)
+{
+ unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+ unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+ __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ & ~(1 << bit), LS1X_INTC_INTIEN(n));
+ __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+ | (1 << bit), LS1X_INTC_INTCLR(n));
+}
+
+static void ls1x_irq_unmask(struct irq_data *d)
+{
+ unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+ unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+ __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ | (1 << bit), LS1X_INTC_INTIEN(n));
+}
+
+static struct irq_chip ls1x_irq_chip = {
+ .name = "LS1X-INTC",
+ .irq_ack = ls1x_irq_ack,
+ .irq_mask = ls1x_irq_mask,
+ .irq_mask_ack = ls1x_irq_mask_ack,
+ .irq_unmask = ls1x_irq_unmask,
+};
+
+static void ls1x_irq_dispatch(int n)
+{
+ u32 int_status, irq;
+
+ /* Get pending sources, masked by current enables */
+ int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
+ __raw_readl(LS1X_INTC_INTIEN(n));
+
+ if (int_status) {
+ irq = LS1X_IRQ(n, __ffs(int_status));
+ do_IRQ(irq);
+ }
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int pending;
+
+ pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+ if (pending & CAUSEF_IP7)
+ do_IRQ(TIMER_IRQ);
+ else if (pending & CAUSEF_IP2)
+ ls1x_irq_dispatch(0); /* INT0 */
+ else if (pending & CAUSEF_IP3)
+ ls1x_irq_dispatch(1); /* INT1 */
+ else if (pending & CAUSEF_IP4)
+ ls1x_irq_dispatch(2); /* INT2 */
+ else if (pending & CAUSEF_IP5)
+ ls1x_irq_dispatch(3); /* INT3 */
+ else if (pending & CAUSEF_IP6)
+ ls1x_irq_dispatch(4); /* INT4 */
+ else
+ spurious_interrupt();
+
+}
+
+struct irqaction cascade_irqaction = {
+ .handler = no_action,
+ .name = "cascade",
+ .flags = IRQF_NO_THREAD,
+};
+
+static void __init ls1x_irq_init(int base)
+{
+ int n;
+
+ /* Disable interrupts and clear pending,
+ * setup all IRQs as high level triggered
+ */
+ for (n = 0; n < 4; n++) {
+ __raw_writel(0x0, LS1X_INTC_INTIEN(n));
+ __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
+ __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
+ __raw_writel(0x0, LS1X_INTC_INTEDGE(n));
+ }
+
+
+ for (n = base; n < NR_IRQS; n++) {
+ irq_set_chip_and_handler(n, &ls1x_irq_chip,
+ handle_level_irq);
+ }
+
+ setup_irq(INT0_IRQ, &cascade_irqaction);
+ setup_irq(INT1_IRQ, &cascade_irqaction);
+ setup_irq(INT2_IRQ, &cascade_irqaction);
+ setup_irq(INT3_IRQ, &cascade_irqaction);
+}
+
+void __init arch_init_irq(void)
+{
+ mips_cpu_irq_init();
+ ls1x_irq_init(LS1X_IRQ_BASE);
+}
diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c
new file mode 100644
index 0000000..2256d40
--- /dev/null
+++ b/arch/mips/loongson1/common/platform.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/phy.h>
+#include <linux/serial_8250.h>
+#include <linux/stmmac.h>
+#include <asm-generic/sizes.h>
+
+#include <loongson1.h>
+
+#define LS1X_UART(_id) \
+ { \
+ .mapbase = LS1X_UART ## _id ## _BASE, \
+ .irq = LS1X_UART ## _id ## _IRQ, \
+ .iotype = UPIO_MEM, \
+ .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
+ .type = PORT_16550A, \
+ }
+
+static struct plat_serial8250_port ls1x_serial8250_port[] = {
+ LS1X_UART(0),
+ LS1X_UART(1),
+ LS1X_UART(2),
+ LS1X_UART(3),
+ {},
+};
+
+struct platform_device ls1x_uart_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = ls1x_serial8250_port,
+ },
+};
+
+void __init ls1x_serial_setup(void)
+{
+ struct clk *clk;
+ struct plat_serial8250_port *p;
+
+ clk = clk_get(NULL, "dc");
+ if (IS_ERR(clk))
+ panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+
+ for (p = ls1x_serial8250_port; p->flags != 0; ++p)
+ p->uartclk = clk_get_rate(clk);
+}
+
+/* Synopsys Ethernet GMAC */
+static struct resource ls1x_eth0_resources[] = {
+ [0] = {
+ .start = LS1X_GMAC0_BASE,
+ .end = LS1X_GMAC0_BASE + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "macirq",
+ .start = LS1X_GMAC0_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
+ .bus_id = 0,
+ .phy_mask = 0,
+};
+
+static struct plat_stmmacenet_data ls1x_eth_data = {
+ .bus_id = 0,
+ .phy_addr = -1,
+ .mdio_bus_data = &ls1x_mdio_bus_data,
+ .pbl = 32,
+ .has_gmac = 1,
+ .enh_desc = 1,
+ .tx_coe = 1,
+};
+
+struct platform_device ls1x_eth0_device = {
+ .name = "stmmaceth",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ls1x_eth0_resources),
+ .resource = ls1x_eth0_resources,
+ .dev = {
+ .platform_data = &ls1x_eth_data,
+ },
+};
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
new file mode 100644
index 0000000..7e2f840
--- /dev/null
+++ b/arch/mips/loongson1/common/prom.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Modified from arch/mips/pnx833x/common/prom.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/bootinfo.h>
+
+#include <loongson1.h>
+#include <prom.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+unsigned long memsize, highmemsize;
+
+char *prom_getenv(char *envname)
+{
+ char **env = prom_envp;
+ int i;
+
+ i = strlen(envname);
+
+ while (*env) {
+ if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
+ return *env + i + 1;
+ env++;
+ }
+
+ return 0;
+}
+
+static inline unsigned long env_or_default(char *env, unsigned long dfl)
+{
+ char *str = prom_getenv(env);
+ return str ? simple_strtol(str, 0, 0) : dfl;
+}
+
+void __init prom_init_cmdline(void)
+{
+ char *c = &(arcs_cmdline[0]);
+ int i;
+
+ for (i = 1; i < prom_argc; i++) {
+ strcpy(c, prom_argv[i]);
+ c += strlen(prom_argv[i]);
+ if (i < prom_argc-1)
+ *c++ = ' ';
+ }
+ *c = 0;
+}
+
+void __init prom_init(void)
+{
+ prom_argc = fw_arg0;
+ prom_argv = (char **)fw_arg1;
+ prom_envp = (char **)fw_arg2;
+
+ prom_init_cmdline();
+
+ memsize = env_or_default("memsize", DEFAULT_MEMSIZE);
+ highmemsize = env_or_default("highmemsize", 0x0);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define UART_BASE LS1X_UART0_BASE
+#define PORT(base, offset) (u8 *)ioremap(base + offset, 1)
+
+void __init prom_putchar(char c)
+{
+ int timeout;
+
+ timeout = 1024;
+
+ while (((readb(PORT(UART_BASE, UART_LSR)) & UART_LSR_THRE) == 0)
+ && (timeout-- > 0))
+ ;
+
+ writeb(c, PORT(UART_BASE, UART_TX));
+}
diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c
new file mode 100644
index 0000000..c913c56
--- /dev/null
+++ b/arch/mips/loongson1/common/reset.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+
+#include <loongson1.h>
+
+static void ls1x_restart(char *command)
+{
+ __raw_writel(0x1, LS1X_WDT_EN);
+ __raw_writel(0x5000000, LS1X_WDT_TIMER);
+ __raw_writel(0x1, LS1X_WDT_SET);
+}
+
+static void ls1x_halt(void)
+{
+ pr_notice("\n\n** You can safely turn off the power now **\n\n");
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static void ls1x_power_off(void)
+{
+ ls1x_halt();
+}
+
+static int __init ls1x_reboot_setup(void)
+{
+ _machine_restart = ls1x_restart;
+ _machine_halt = ls1x_halt;
+ pm_power_off = ls1x_power_off;
+
+ return 0;
+}
+
+arch_initcall(ls1x_reboot_setup);
diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c
new file mode 100644
index 0000000..62128cc
--- /dev/null
+++ b/arch/mips/loongson1/common/setup.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <asm/bootinfo.h>
+
+#include <prom.h>
+
+void __init plat_mem_setup(void)
+{
+ add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+}
+
+const char *get_system_type(void)
+{
+ unsigned int processor_id = (¤t_cpu_data)->processor_id;
+
+ switch (processor_id & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON1B:
+ return "LOONGSON LS1B";
+ default:
+ return "LOONGSON (unknown)";
+ }
+}
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
new file mode 100644
index 0000000..dd4cd9c
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <platform.h>
+
+#include <linux/serial_8250.h>
+#include <loongson1.h>
+
+static struct platform_device *ls1b_platform_devices[] __initdata = {
+ &ls1x_uart_device,
+ &ls1x_eth0_device,
+};
+
+static int __init ls1b_platform_init(void)
+{
+ int err;
+
+ ls1x_serial_setup();
+
+ err = platform_add_devices(ls1b_platform_devices,
+ ARRAY_SIZE(ls1b_platform_devices));
+ return err;
+}
+
+arch_initcall(ls1b_platform_init);
diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
index 63a03e2..4db27d0 100644
--- a/drivers/net/stmmac/descs.h
+++ b/drivers/net/stmmac/descs.h
@@ -53,6 +53,38 @@ struct dma_desc {
u32 reserved3:5;
u32 disable_ic:1;
} rx;
+#ifdef CONFIG_MACH_LOONGSON1
+ struct {
+ /* RDES0 */
+ u32 payload_csum_error:1;
+ u32 crc_error:1;
+ u32 dribbling:1;
+ u32 error_gmii:1;
+ u32 receive_watchdog:1;
+ u32 frame_type:1;
+ u32 late_collision:1;
+ u32 ipc_csum_error:1;
+ u32 last_descriptor:1;
+ u32 first_descriptor:1;
+ u32 vlan_tag:1;
+ u32 overflow_error:1;
+ u32 length_error:1;
+ u32 sa_filter_fail:1;
+ u32 descriptor_error:1;
+ u32 error_summary:1;
+ u32 frame_length:14;
+ u32 da_filter_fail:1;
+ u32 own:1;
+ /* RDES1 */
+ u32 buffer1_size:11;
+ u32 buffer2_size:11;
+ u32 reserved1:2;
+ u32 second_address_chained:1;
+ u32 end_ring:1;
+ u32 reserved2:5;
+ u32 disable_ic:1;
+ } erx; /* -- enhanced -- */
+#else
struct {
/* RDES0 */
u32 payload_csum_error:1;
@@ -83,6 +115,7 @@ struct dma_desc {
u32 reserved2:2;
u32 disable_ic:1;
} erx; /* -- enhanced -- */
+#endif
/* Transmit descriptor */
struct {
@@ -113,6 +146,40 @@ struct dma_desc {
u32 last_segment:1;
u32 interrupt:1;
} tx;
+#ifdef CONFIG_MACH_LOONGSON1
+ struct {
+ /* TDES0 */
+ u32 deferred:1;
+ u32 underflow_error:1;
+ u32 excessive_deferral:1;
+ u32 collision_count:4;
+ u32 vlan_frame:1;
+ u32 excessive_collisions:1;
+ u32 late_collision:1;
+ u32 no_carrier:1;
+ u32 loss_carrier:1;
+ u32 payload_error:1;
+ u32 frame_flushed:1;
+ u32 jabber_timeout:1;
+ u32 error_summary:1;
+ u32 ip_header_error:1;
+ u32 time_stamp_status:1;
+ u32 reserved1:13;
+ u32 own:1;
+ /* TDES1 */
+ u32 buffer1_size:11;
+ u32 buffer2_size:11;
+ u32 time_stamp_enable:1;
+ u32 disable_padding:1;
+ u32 second_address_chained:1;
+ u32 end_ring:1;
+ u32 crc_disable:1;
+ u32 checksum_insertion:2;
+ u32 first_segment:1;
+ u32 last_segment:1;
+ u32 interrupt:1;
+ } etx; /* -- enhanced -- */
+#else
struct {
/* TDES0 */
u32 deferred:1;
@@ -148,6 +215,7 @@ struct dma_desc {
u32 buffer2_size:13;
u32 reserved4:3;
} etx; /* -- enhanced -- */
+#endif
} des01;
unsigned int des2;
unsigned int des3;
diff --git a/drivers/net/stmmac/enh_desc.c b/drivers/net/stmmac/enh_desc.c
index e5dfb6a..3b5e4f1 100644
--- a/drivers/net/stmmac/enh_desc.c
+++ b/drivers/net/stmmac/enh_desc.c
@@ -108,6 +108,7 @@ static int enh_desc_get_tx_len(struct dma_desc *p)
static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
{
int ret = good_frame;
+#ifndef CONFIG_MACH_LOONGSON1
u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
/* bits 5 7 0 | Frame status
@@ -145,6 +146,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
CHIP_DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
ret = discard_frame;
}
+#endif
return ret;
}
@@ -232,9 +234,17 @@ static void enh_desc_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
int i;
for (i = 0; i < ring_size; i++) {
p->des01.erx.own = 1;
+#ifdef CONFIG_MACH_LOONGSON1
+ p->des01.erx.buffer1_size = BUF_SIZE_2KiB - 1;
+#else
p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
+#endif
/* To support jumbo frames */
+#ifdef CONFIG_MACH_LOONGSON1
+ p->des01.erx.buffer2_size = BUF_SIZE_2KiB - 1;
+#else
p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
+#endif
if (i == ring_size - 1)
p->des01.erx.end_ring = 1;
if (disable_rx_ic)
@@ -292,9 +302,15 @@ static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
int csum_flag)
{
p->des01.etx.first_segment = is_fs;
+#ifdef CONFIG_MACH_LOONGSON1
+ if (unlikely(len > BUF_SIZE_2KiB)) {
+ p->des01.etx.buffer1_size = BUF_SIZE_2KiB - 1;
+ p->des01.etx.buffer2_size = len - BUF_SIZE_2KiB + 1;
+#else
if (unlikely(len > BUF_SIZE_4KiB)) {
p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
+#endif
} else {
p->des01.etx.buffer1_size = len;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V2 3/4] MIPS: Add Makefile and Kconfig for Loongson1B
2011-10-21 10:28 [PATCH V2 1/4] MIPS: Add CPU support for Loongson1B keguang.zhang
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
@ 2011-10-21 10:28 ` keguang.zhang
2011-10-21 10:28 ` [PATCH V2 4/4] MIPS: Add defconfig " keguang.zhang
2 siblings, 0 replies; 19+ messages in thread
From: keguang.zhang @ 2011-10-21 10:28 UTC (permalink / raw)
To: linux-mips, linux-kernel; +Cc: ralf, wuzhangjin, r0bertz, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch adds Makefile and Kconfig related to Loongson1B.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 31 +++++++++++++++++++++++++++++++
arch/mips/loongson1/Kconfig | 21 +++++++++++++++++++++
arch/mips/loongson1/Makefile | 11 +++++++++++
arch/mips/loongson1/Platform | 7 +++++++
arch/mips/loongson1/common/Makefile | 5 +++++
arch/mips/loongson1/ls1b/Makefile | 5 +++++
7 files changed, 81 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/loongson1/Kconfig
create mode 100644 arch/mips/loongson1/Makefile
create mode 100644 arch/mips/loongson1/Platform
create mode 100644 arch/mips/loongson1/common/Makefile
create mode 100644 arch/mips/loongson1/ls1b/Makefile
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..d64786d 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
platforms += lantiq
platforms += lasat
platforms += loongson
+platforms += loongson1
platforms += mipssim
platforms += mti-malta
platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d9b8ea8..4c6ad4f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -262,6 +262,17 @@ config MACH_LOONGSON
Chinese Academy of Sciences (CAS) in the People's Republic
of China. The chief architect is Professor Weiwu Hu.
+config MACH_LOONGSON1
+ bool "Loongson1 family of machines"
+ select SYS_SUPPORTS_ZBOOT
+ help
+ This enables the support of Loongson1 family of machines.
+
+ Loongson1 is a family of 32-bit MIPS-compatible SoCs.
+ developed at Institute of Computing Technology (ICT),
+ Chinese Academy of Sciences (CAS) in the People's Republic
+ of China.
+
config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -808,6 +819,7 @@ source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
source "arch/mips/loongson/Kconfig"
+source "arch/mips/loongson1/Kconfig"
source "arch/mips/netlogic/Kconfig"
endmenu
@@ -1201,6 +1213,14 @@ config CPU_LOONGSON2F
have a similar programming interface with FPGA northbridge used in
Loongson2E.
+config CPU_LOONGSON1B
+ bool "Loongson 1B"
+ depends on SYS_HAS_CPU_LOONGSON1B
+ select CPU_LOONGSON1
+ help
+ The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1529,6 +1549,14 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
+config CPU_LOONGSON1
+ bool
+ select CPU_MIPS32
+ select CPU_MIPSR2
+ select CPU_HAS_PREFETCH
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+
config SYS_HAS_CPU_LOONGSON2E
bool
@@ -1538,6 +1566,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
+config SYS_HAS_CPU_LOONGSON1B
+ bool
+
config SYS_HAS_CPU_MIPS32_R1
bool
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 0000000..237fa21
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
+if MACH_LOONGSON1
+
+choice
+ prompt "Machine Type"
+
+config LOONGSON1_LS1B
+ bool "Loongson LS1B board"
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_LOONGSON1B
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select IRQ_CPU
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 0000000..e9123c2
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 0000000..92804c6
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1) += \
+ $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+ -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1) += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1
+load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80010000
diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile
new file mode 100644
index 0000000..b279770
--- /dev/null
+++ b/arch/mips/loongson1/common/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for common code of loongson1 based machines.
+#
+
+obj-y += clock.o irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile
new file mode 100644
index 0000000..891eac4
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for loongson1B based machines.
+#
+
+obj-y += board.o
--
1.7.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V2 4/4] MIPS: Add defconfig for Loongson1B
2011-10-21 10:28 [PATCH V2 1/4] MIPS: Add CPU support for Loongson1B keguang.zhang
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
2011-10-21 10:28 ` [PATCH V2 3/4] MIPS: Add Makefile and Kconfig " keguang.zhang
@ 2011-10-21 10:28 ` keguang.zhang
2 siblings, 0 replies; 19+ messages in thread
From: keguang.zhang @ 2011-10-21 10:28 UTC (permalink / raw)
To: linux-mips, linux-kernel; +Cc: ralf, wuzhangjin, r0bertz, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch adds defconfig for Loongson1B.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
arch/mips/configs/ls1b_defconfig | 89 ++++++++++++++++++++++++++++++++++++++
1 files changed, 89 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/configs/ls1b_defconfig
diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 0000000..9294ea0
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,89 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TINY_RCU=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_RAMOOPS=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
--
1.7.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
@ 2011-10-21 17:33 ` Wu Zhangjin
2011-10-24 7:19 ` Giuseppe CAVALLARO
2011-11-16 14:10 ` Ralf Baechle
1 sibling, 1 reply; 19+ messages in thread
From: Wu Zhangjin @ 2011-10-21 17:33 UTC (permalink / raw)
To: keguang.zhang; +Cc: linux-mips, linux-kernel, ralf, r0bertz, netdev
On Fri, Oct 21, 2011 at 6:28 PM, <keguang.zhang@gmail.com> wrote:
> From: Kelvin Cheung <keguang.zhang@gmail.com>
>
> This patch adds basic platform support for Loongson1B
> including serial port, ethernet, and interrupt handler.
>
> Loongson1B UART is compatible with NS16550A.
> Loongson1B GMAC is built around Synopsys IP Core.
>
Perhaps you'd better split out the GMAC support to its own patch and
send it to the net/ maintainer and the authors of the original files.
> diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
> index 63a03e2..4db27d0 100644
> --- a/drivers/net/stmmac/descs.h
> +++ b/drivers/net/stmmac/descs.h
> @@ -53,6 +53,38 @@ struct dma_desc {
> u32 reserved3:5;
> u32 disable_ic:1;
> } rx;
> +#ifdef CONFIG_MACH_LOONGSON1
> + struct {
> + /* RDES0 */
> + u32 payload_csum_error:1;
> + u32 crc_error:1;
> + u32 dribbling:1;
> + u32 error_gmii:1;
> + u32 receive_watchdog:1;
> + u32 frame_type:1;
> + u32 late_collision:1;
> + u32 ipc_csum_error:1;
> + u32 last_descriptor:1;
> + u32 first_descriptor:1;
> + u32 vlan_tag:1;
> + u32 overflow_error:1;
> + u32 length_error:1;
> + u32 sa_filter_fail:1;
> + u32 descriptor_error:1;
> + u32 error_summary:1;
> + u32 frame_length:14;
> + u32 da_filter_fail:1;
> + u32 own:1;
> + /* RDES1 */
> + u32 buffer1_size:11;
> + u32 buffer2_size:11;
> + u32 reserved1:2;
> + u32 second_address_chained:1;
> + u32 end_ring:1;
> + u32 reserved2:5;
> + u32 disable_ic:1;
> + } erx; /* -- enhanced -- */
> +#else
> struct {
> /* RDES0 */
> u32 payload_csum_error:1;
> @@ -83,6 +115,7 @@ struct dma_desc {
> u32 reserved2:2;
> u32 disable_ic:1;
> } erx; /* -- enhanced -- */
> +#endif
>
> /* Transmit descriptor */
> struct {
> @@ -113,6 +146,40 @@ struct dma_desc {
> u32 last_segment:1;
> u32 interrupt:1;
> } tx;
> +#ifdef CONFIG_MACH_LOONGSON1
> + struct {
> + /* TDES0 */
> + u32 deferred:1;
> + u32 underflow_error:1;
> + u32 excessive_deferral:1;
> + u32 collision_count:4;
> + u32 vlan_frame:1;
> + u32 excessive_collisions:1;
> + u32 late_collision:1;
> + u32 no_carrier:1;
> + u32 loss_carrier:1;
> + u32 payload_error:1;
> + u32 frame_flushed:1;
> + u32 jabber_timeout:1;
> + u32 error_summary:1;
> + u32 ip_header_error:1;
> + u32 time_stamp_status:1;
> + u32 reserved1:13;
> + u32 own:1;
> + /* TDES1 */
> + u32 buffer1_size:11;
> + u32 buffer2_size:11;
> + u32 time_stamp_enable:1;
> + u32 disable_padding:1;
> + u32 second_address_chained:1;
> + u32 end_ring:1;
> + u32 crc_disable:1;
> + u32 checksum_insertion:2;
> + u32 first_segment:1;
> + u32 last_segment:1;
> + u32 interrupt:1;
> + } etx; /* -- enhanced -- */
> +#else
> struct {
> /* TDES0 */
> u32 deferred:1;
> @@ -148,6 +215,7 @@ struct dma_desc {
> u32 buffer2_size:13;
> u32 reserved4:3;
> } etx; /* -- enhanced -- */
> +#endif
> } des01;
> unsigned int des2;
> unsigned int des3;
If the difference is very much, perhaps a new dma_desc struct can be
defined instead.
> diff --git a/drivers/net/stmmac/enh_desc.c b/drivers/net/stmmac/enh_desc.c
> index e5dfb6a..3b5e4f1 100644
> --- a/drivers/net/stmmac/enh_desc.c
> +++ b/drivers/net/stmmac/enh_desc.c
> @@ -108,6 +108,7 @@ static int enh_desc_get_tx_len(struct dma_desc *p)
> static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
> {
> int ret = good_frame;
> +#ifndef CONFIG_MACH_LOONGSON1
> u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
>
> /* bits 5 7 0 | Frame status
> @@ -145,6 +146,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
> CHIP_DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
> ret = discard_frame;
> }
> +#endif
> return ret;
> }
>
> @@ -232,9 +234,17 @@ static void enh_desc_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
> int i;
> for (i = 0; i < ring_size; i++) {
> p->des01.erx.own = 1;
> +#ifdef CONFIG_MACH_LOONGSON1
> + p->des01.erx.buffer1_size = BUF_SIZE_2KiB - 1;
> +#else
> p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
> +#endif
> /* To support jumbo frames */
> +#ifdef CONFIG_MACH_LOONGSON1
> + p->des01.erx.buffer2_size = BUF_SIZE_2KiB - 1;
> +#else
> p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
> +#endif
> if (i == ring_size - 1)
> p->des01.erx.end_ring = 1;
> if (disable_rx_ic)
> @@ -292,9 +302,15 @@ static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
> int csum_flag)
> {
> p->des01.etx.first_segment = is_fs;
> +#ifdef CONFIG_MACH_LOONGSON1
> + if (unlikely(len > BUF_SIZE_2KiB)) {
> + p->des01.etx.buffer1_size = BUF_SIZE_2KiB - 1;
> + p->des01.etx.buffer2_size = len - BUF_SIZE_2KiB + 1;
> +#else
> if (unlikely(len > BUF_SIZE_4KiB)) {
> p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
> p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
> +#endif
> } else {
> p->des01.etx.buffer1_size = len;
> }
Is it possible to add two new macros RX_BUF_SIZE and TX_BUF_SIZE to .h
instead? which may reduce code duplication.
Regards,
Wu Zhangjin
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-21 17:33 ` Wu Zhangjin
@ 2011-10-24 7:19 ` Giuseppe CAVALLARO
2011-10-24 10:36 ` Kelvin Cheung
0 siblings, 1 reply; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-24 7:19 UTC (permalink / raw)
To: keguang.zhang
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
On 10/21/2011 7:33 PM, Wu Zhangjin wrote:
> On Fri, Oct 21, 2011 at 6:28 PM, <keguang.zhang@gmail.com> wrote:
>> From: Kelvin Cheung <keguang.zhang@gmail.com>
>>
>> This patch adds basic platform support for Loongson1B
>> including serial port, ethernet, and interrupt handler.
>>
>> Loongson1B UART is compatible with NS16550A.
>> Loongson1B GMAC is built around Synopsys IP Core.
>>
>
> Perhaps you'd better split out the GMAC support to its own patch and
> send it to the net/ maintainer and the authors of the original files.
Also suggest you to provide the stmmac patches for net-next.
The stmmac driver has been recently updated and I've also several
patches to commit (for example for PCI etc) on it.
I'm happy that the support for big endianess arrived.
I supported a guy some time ago but he didn't provided me the patches
tested on his side :-(. So welcome yours and many thanks Kelvin!
Please send the stmmac patches and add me on CC. I'm happy to help you
on reviewing them.
>> diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
>> index 63a03e2..4db27d0 100644
>> --- a/drivers/net/stmmac/descs.h
>> +++ b/drivers/net/stmmac/descs.h
>> @@ -53,6 +53,38 @@ struct dma_desc {
>> u32 reserved3:5;
>> u32 disable_ic:1;
>> } rx;
>> +#ifdef CONFIG_MACH_LOONGSON1
>> + struct {
>> + /* RDES0 */
>> + u32 payload_csum_error:1;
>> + u32 crc_error:1;
>> + u32 dribbling:1;
>> + u32 error_gmii:1;
>> + u32 receive_watchdog:1;
>> + u32 frame_type:1;
>> + u32 late_collision:1;
>> + u32 ipc_csum_error:1;
>> + u32 last_descriptor:1;
>> + u32 first_descriptor:1;
>> + u32 vlan_tag:1;
>> + u32 overflow_error:1;
>> + u32 length_error:1;
>> + u32 sa_filter_fail:1;
>> + u32 descriptor_error:1;
>> + u32 error_summary:1;
>> + u32 frame_length:14;
>> + u32 da_filter_fail:1;
>> + u32 own:1;
>> + /* RDES1 */
>> + u32 buffer1_size:11;
>> + u32 buffer2_size:11;
>> + u32 reserved1:2;
>> + u32 second_address_chained:1;
>> + u32 end_ring:1;
>> + u32 reserved2:5;
>> + u32 disable_ic:1;
>> + } erx; /* -- enhanced -- */
>> +#else
>> struct {
>> /* RDES0 */
>> u32 payload_csum_error:1;
>> @@ -83,6 +115,7 @@ struct dma_desc {
>> u32 reserved2:2;
>> u32 disable_ic:1;
>> } erx; /* -- enhanced -- */
>> +#endif
>>
>> /* Transmit descriptor */
>> struct {
>> @@ -113,6 +146,40 @@ struct dma_desc {
>> u32 last_segment:1;
>> u32 interrupt:1;
>> } tx;
>> +#ifdef CONFIG_MACH_LOONGSON1
>> + struct {
>> + /* TDES0 */
>> + u32 deferred:1;
>> + u32 underflow_error:1;
>> + u32 excessive_deferral:1;
>> + u32 collision_count:4;
>> + u32 vlan_frame:1;
>> + u32 excessive_collisions:1;
>> + u32 late_collision:1;
>> + u32 no_carrier:1;
>> + u32 loss_carrier:1;
>> + u32 payload_error:1;
>> + u32 frame_flushed:1;
>> + u32 jabber_timeout:1;
>> + u32 error_summary:1;
>> + u32 ip_header_error:1;
>> + u32 time_stamp_status:1;
>> + u32 reserved1:13;
>> + u32 own:1;
>> + /* TDES1 */
>> + u32 buffer1_size:11;
>> + u32 buffer2_size:11;
>> + u32 time_stamp_enable:1;
>> + u32 disable_padding:1;
>> + u32 second_address_chained:1;
>> + u32 end_ring:1;
>> + u32 crc_disable:1;
>> + u32 checksum_insertion:2;
>> + u32 first_segment:1;
>> + u32 last_segment:1;
>> + u32 interrupt:1;
>> + } etx; /* -- enhanced -- */
>> +#else
>> struct {
>> /* TDES0 */
>> u32 deferred:1;
>> @@ -148,6 +215,7 @@ struct dma_desc {
>> u32 buffer2_size:13;
>> u32 reserved4:3;
>> } etx; /* -- enhanced -- */
>> +#endif
>> } des01;
>> unsigned int des2;
>> unsigned int des3;
>
>
> If the difference is very much, perhaps a new dma_desc struct can be
> defined instead.
>
Concerning the descriptors, we could have two different files:
descs_le.h
descs_be.h
and select their inclusion inside the common.h.
Please use instead of the macro CONFIG_MACH_LOONGSON1 another one more
generic e.g. CONFIG_STMMAC_BE (and add it in the driver's Kconfig).
On your platform you will have to enable it by default.
Or it could be the default on MIPS: LE will be on ARM and SuperH.
>> diff --git a/drivers/net/stmmac/enh_desc.c b/drivers/net/stmmac/enh_desc.c
>> index e5dfb6a..3b5e4f1 100644
>> --- a/drivers/net/stmmac/enh_desc.c
>> +++ b/drivers/net/stmmac/enh_desc.c
>> @@ -108,6 +108,7 @@ static int enh_desc_get_tx_len(struct dma_desc *p)
>> static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
>> {
>> int ret = good_frame;
>> +#ifndef CONFIG_MACH_LOONGSON1
>> u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
>>
>> /* bits 5 7 0 | Frame status
>> @@ -145,6 +146,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
>> CHIP_DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
>> ret = discard_frame;
>> }
>> +#endif
>> return ret;
>> }
>>
>> @@ -232,9 +234,17 @@ static void enh_desc_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
>> int i;
>> for (i = 0; i < ring_size; i++) {
>> p->des01.erx.own = 1;
>> +#ifdef CONFIG_MACH_LOONGSON1
>> + p->des01.erx.buffer1_size = BUF_SIZE_2KiB - 1;
>> +#else
>> p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
>> +#endif
>> /* To support jumbo frames */
>> +#ifdef CONFIG_MACH_LOONGSON1
>> + p->des01.erx.buffer2_size = BUF_SIZE_2KiB - 1;
>> +#else
>> p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
>> +#endif
>> if (i == ring_size - 1)
>> p->des01.erx.end_ring = 1;
>> if (disable_rx_ic)
>> @@ -292,9 +302,15 @@ static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
>> int csum_flag)
>> {
>> p->des01.etx.first_segment = is_fs;
>> +#ifdef CONFIG_MACH_LOONGSON1
>> + if (unlikely(len > BUF_SIZE_2KiB)) {
>> + p->des01.etx.buffer1_size = BUF_SIZE_2KiB - 1;
>> + p->des01.etx.buffer2_size = len - BUF_SIZE_2KiB + 1;
>> +#else
>> if (unlikely(len > BUF_SIZE_4KiB)) {
>> p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
>> p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
>> +#endif
>> } else {
>> p->des01.etx.buffer1_size = len;
>> }
No. I do not want to see all these ifdef inside the code.
I had to rework some driver's part just last week to avoid this kind of
code. I suggest you to re-base the work against the net-next kernel and
look at how the ring/chained modes have been managed.
I added a new file called descs_com.h that you can re-use adding small
inline functions where define the changes for be mode.
> Is it possible to add two new macros RX_BUF_SIZE and TX_BUF_SIZE to .h
> instead? which may reduce code duplication.
This code exists because we have to properly handle the jumbo frames.
Note that this code has been reworked to use the ring/chained modes.
Take a look at descs_com.h.
I expect to see the driver on your platform that uses jumbo and
chained/ring modes.
Best Regards
Giuseppe
>
> Regards,
> Wu Zhangjin
>
>> --
>> 1.7.1
>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-24 7:19 ` Giuseppe CAVALLARO
@ 2011-10-24 10:36 ` Kelvin Cheung
2011-10-24 12:18 ` Giuseppe CAVALLARO
0 siblings, 1 reply; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-24 10:36 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
Hi Giuseppe,
2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> On 10/21/2011 7:33 PM, Wu Zhangjin wrote:
>> On Fri, Oct 21, 2011 at 6:28 PM, <keguang.zhang@gmail.com> wrote:
>>> From: Kelvin Cheung <keguang.zhang@gmail.com>
>>>
>>> This patch adds basic platform support for Loongson1B
>>> including serial port, ethernet, and interrupt handler.
>>>
>>> Loongson1B UART is compatible with NS16550A.
>>> Loongson1B GMAC is built around Synopsys IP Core.
>>>
>>
>> Perhaps you'd better split out the GMAC support to its own patch and
>> send it to the net/ maintainer and the authors of the original files.
>
> Also suggest you to provide the stmmac patches for net-next.
> The stmmac driver has been recently updated and I've also several
> patches to commit (for example for PCI etc) on it.
>
> I'm happy that the support for big endianess arrived.
> I supported a guy some time ago but he didn't provided me the patches
> tested on his side :-(. So welcome yours and many thanks Kelvin!
>
> Please send the stmmac patches and add me on CC. I'm happy to help you
> on reviewing them.
Thanks for your review.
>>> diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
>>> index 63a03e2..4db27d0 100644
>>> --- a/drivers/net/stmmac/descs.h
>>> +++ b/drivers/net/stmmac/descs.h
>>> @@ -53,6 +53,38 @@ struct dma_desc {
>>> u32 reserved3:5;
>>> u32 disable_ic:1;
>>> } rx;
>>> +#ifdef CONFIG_MACH_LOONGSON1
>>> + struct {
>>> + /* RDES0 */
>>> + u32 payload_csum_error:1;
>>> + u32 crc_error:1;
>>> + u32 dribbling:1;
>>> + u32 error_gmii:1;
>>> + u32 receive_watchdog:1;
>>> + u32 frame_type:1;
>>> + u32 late_collision:1;
>>> + u32 ipc_csum_error:1;
>>> + u32 last_descriptor:1;
>>> + u32 first_descriptor:1;
>>> + u32 vlan_tag:1;
>>> + u32 overflow_error:1;
>>> + u32 length_error:1;
>>> + u32 sa_filter_fail:1;
>>> + u32 descriptor_error:1;
>>> + u32 error_summary:1;
>>> + u32 frame_length:14;
>>> + u32 da_filter_fail:1;
>>> + u32 own:1;
>>> + /* RDES1 */
>>> + u32 buffer1_size:11;
>>> + u32 buffer2_size:11;
>>> + u32 reserved1:2;
>>> + u32 second_address_chained:1;
>>> + u32 end_ring:1;
>>> + u32 reserved2:5;
>>> + u32 disable_ic:1;
>>> + } erx; /* -- enhanced -- */
>>> +#else
>>> struct {
>>> /* RDES0 */
>>> u32 payload_csum_error:1;
>>> @@ -83,6 +115,7 @@ struct dma_desc {
>>> u32 reserved2:2;
>>> u32 disable_ic:1;
>>> } erx; /* -- enhanced -- */
>>> +#endif
>>>
>>> /* Transmit descriptor */
>>> struct {
>>> @@ -113,6 +146,40 @@ struct dma_desc {
>>> u32 last_segment:1;
>>> u32 interrupt:1;
>>> } tx;
>>> +#ifdef CONFIG_MACH_LOONGSON1
>>> + struct {
>>> + /* TDES0 */
>>> + u32 deferred:1;
>>> + u32 underflow_error:1;
>>> + u32 excessive_deferral:1;
>>> + u32 collision_count:4;
>>> + u32 vlan_frame:1;
>>> + u32 excessive_collisions:1;
>>> + u32 late_collision:1;
>>> + u32 no_carrier:1;
>>> + u32 loss_carrier:1;
>>> + u32 payload_error:1;
>>> + u32 frame_flushed:1;
>>> + u32 jabber_timeout:1;
>>> + u32 error_summary:1;
>>> + u32 ip_header_error:1;
>>> + u32 time_stamp_status:1;
>>> + u32 reserved1:13;
>>> + u32 own:1;
>>> + /* TDES1 */
>>> + u32 buffer1_size:11;
>>> + u32 buffer2_size:11;
>>> + u32 time_stamp_enable:1;
>>> + u32 disable_padding:1;
>>> + u32 second_address_chained:1;
>>> + u32 end_ring:1;
>>> + u32 crc_disable:1;
>>> + u32 checksum_insertion:2;
>>> + u32 first_segment:1;
>>> + u32 last_segment:1;
>>> + u32 interrupt:1;
>>> + } etx; /* -- enhanced -- */
>>> +#else
>>> struct {
>>> /* TDES0 */
>>> u32 deferred:1;
>>> @@ -148,6 +215,7 @@ struct dma_desc {
>>> u32 buffer2_size:13;
>>> u32 reserved4:3;
>>> } etx; /* -- enhanced -- */
>>> +#endif
>>> } des01;
>>> unsigned int des2;
>>> unsigned int des3;
>>
>>
>> If the difference is very much, perhaps a new dma_desc struct can be
>> defined instead.
>>
>
> Concerning the descriptors, we could have two different files:
>
> descs_le.h
> descs_be.h
>
> and select their inclusion inside the common.h.
>
> Please use instead of the macro CONFIG_MACH_LOONGSON1 another one more
> generic e.g. CONFIG_STMMAC_BE (and add it in the driver's Kconfig).
>
> On your platform you will have to enable it by default.
> Or it could be the default on MIPS: LE will be on ARM and SuperH.
Loongson1B(MIPS32 R2 compatible) is little endian.
And as you can see, the bitfield of RX/TX descriptor is different from
the enhanced descriptor.
>>> diff --git a/drivers/net/stmmac/enh_desc.c
>>> b/drivers/net/stmmac/enh_desc.c
>>> index e5dfb6a..3b5e4f1 100644
>>> --- a/drivers/net/stmmac/enh_desc.c
>>> +++ b/drivers/net/stmmac/enh_desc.c
>>> @@ -108,6 +108,7 @@ static int enh_desc_get_tx_len(struct dma_desc *p)
>>> static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
>>> {
>>> int ret = good_frame;
>>> +#ifndef CONFIG_MACH_LOONGSON1
>>> u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
>>>
>>> /* bits 5 7 0 | Frame status
>>> @@ -145,6 +146,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type,
>>> int payload_err)
>>> CHIP_DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6
>>> frame.\n");
>>> ret = discard_frame;
>>> }
>>> +#endif
>>> return ret;
>>> }
>
>>>
>>> @@ -232,9 +234,17 @@ static void enh_desc_init_rx_desc(struct dma_desc
>>> *p, unsigned int ring_size,
>>> int i;
>>> for (i = 0; i < ring_size; i++) {
>>> p->des01.erx.own = 1;
>>> +#ifdef CONFIG_MACH_LOONGSON1
>>> + p->des01.erx.buffer1_size = BUF_SIZE_2KiB - 1;
>>> +#else
>>> p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
>>> +#endif
>>> /* To support jumbo frames */
>>> +#ifdef CONFIG_MACH_LOONGSON1
>>> + p->des01.erx.buffer2_size = BUF_SIZE_2KiB - 1;
>>> +#else
>>> p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
>>> +#endif
>>> if (i == ring_size - 1)
>>> p->des01.erx.end_ring = 1;
>>> if (disable_rx_ic)
>>> @@ -292,9 +302,15 @@ static void enh_desc_prepare_tx_desc(struct dma_desc
>>> *p, int is_fs, int len,
>>> int csum_flag)
>>> {
>>> p->des01.etx.first_segment = is_fs;
>>> +#ifdef CONFIG_MACH_LOONGSON1
>>> + if (unlikely(len > BUF_SIZE_2KiB)) {
>>> + p->des01.etx.buffer1_size = BUF_SIZE_2KiB - 1;
>>> + p->des01.etx.buffer2_size = len - BUF_SIZE_2KiB + 1;
>>> +#else
>>> if (unlikely(len > BUF_SIZE_4KiB)) {
>>> p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
>>> p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
>>> +#endif
>>> } else {
>>> p->des01.etx.buffer1_size = len;
>>> }
>
> No. I do not want to see all these ifdef inside the code.
> I had to rework some driver's part just last week to avoid this kind of
> code. I suggest you to re-base the work against the net-next kernel and
> look at how the ring/chained modes have been managed.
>
> I added a new file called descs_com.h that you can re-use adding small
> inline functions where define the changes for be mode.
According to datasheet of Loongson 1B, the buffer size in RX/TX
descriptor is only 2KB.
So the Loongson1B's GMAC could not handle jumbo frames.
And the second buffer is useless in this case.
Am I right?
Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to avoid duplicate code?
>> Is it possible to add two new macros RX_BUF_SIZE and TX_BUF_SIZE to .h
>> instead? which may reduce code duplication.
>
> This code exists because we have to properly handle the jumbo frames.
>
> Note that this code has been reworked to use the ring/chained modes.
> Take a look at descs_com.h.
>
> I expect to see the driver on your platform that uses jumbo and
> chained/ring modes.
>
> Best Regards
> Giuseppe
>
>>
>> Regards,
>> Wu Zhangjin
>>
>>> --
>>> 1.7.1
>>>
>>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-24 10:36 ` Kelvin Cheung
@ 2011-10-24 12:18 ` Giuseppe CAVALLARO
2011-10-24 14:05 ` Kelvin Cheung
0 siblings, 1 reply; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-24 12:18 UTC (permalink / raw)
To: Kelvin Cheung
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
Hello Kelvin.
On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
[snip]
> According to datasheet of Loongson 1B, the buffer size in RX/TX
> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
> jumbo frames. And the second buffer is useless in this case. Am I
> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
> avoid duplicate code?
Sorry for my misunderstanding.
I think you have to use the normal descriptor and remove the enh_desc
from the platform w/o modifying the driver at all.
The driver will be able to select/configure all automatically (also jumbo).
Let me know.
Note:
IIRC, there is a bit difference in case of normal descriptors for
Synopsys databook newer than the 1.91 (I used for testing this mode).
In any case, I remember that, on some platforms, the normal descriptors
have been used w/o problems also on these new chip generations.
Peppe
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-24 12:18 ` Giuseppe CAVALLARO
@ 2011-10-24 14:05 ` Kelvin Cheung
2011-10-24 15:35 ` Giuseppe CAVALLARO
0 siblings, 1 reply; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-24 14:05 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> Hello Kelvin.
>
> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>
> [snip]
>
>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>> jumbo frames. And the second buffer is useless in this case. Am I
>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>> avoid duplicate code?
>
> Sorry for my misunderstanding.
>
> I think you have to use the normal descriptor and remove the enh_desc
> from the platform w/o modifying the driver at all.
>
> The driver will be able to select/configure all automatically (also jumbo).
>
> Let me know.
That's the problem.
The bitfield definition of Loongson1B is also different from normal descriptor.
Moreover, I want to enable the TX checksum offload function which is
not supported in normal descriptor.
Any suggestions?
> Note:
> IIRC, there is a bit difference in case of normal descriptors for
> Synopsys databook newer than the 1.91 (I used for testing this mode).
> In any case, I remember that, on some platforms, the normal descriptors
> have been used w/o problems also on these new chip generations.
>
> Peppe
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-24 14:05 ` Kelvin Cheung
@ 2011-10-24 15:35 ` Giuseppe CAVALLARO
2011-10-25 2:12 ` Kelvin Cheung
0 siblings, 1 reply; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-24 15:35 UTC (permalink / raw)
To: Kelvin Cheung
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>> Hello Kelvin.
>>
>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>
>> [snip]
>>
>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>> jumbo frames. And the second buffer is useless in this case. Am I
>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>> avoid duplicate code?
>>
>> Sorry for my misunderstanding.
>>
>> I think you have to use the normal descriptor and remove the enh_desc
>> from the platform w/o modifying the driver at all.
>>
>> The driver will be able to select/configure all automatically (also jumbo).
>>
>> Let me know.
>
> That's the problem.
> The bitfield definition of Loongson1B is also different from normal descriptor.
The problem is not in the Loongson1B gmac.
The normal descriptor fields in the stmmac refer to an old synopsys
databook.
New chips have the same structure you have added; so we should fix this
in the driver w/o breaking the compatibility for old chips.
I kindly ask you to confirm if the currently normal descriptor structure
(w/o your changes) doesn't work on your platform.
Did you test it?
> Moreover, I want to enable the TX checksum offload function which is
> not supported in normal descriptor.
> Any suggestions?
It is supported but you have to pass from the platform: tx_coe = 1.
Peppe
>
>> Note:
>> IIRC, there is a bit difference in case of normal descriptors for
>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>> In any case, I remember that, on some platforms, the normal descriptors
>> have been used w/o problems also on these new chip generations.
>>
>> Peppe
>>
>>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-24 15:35 ` Giuseppe CAVALLARO
@ 2011-10-25 2:12 ` Kelvin Cheung
2011-10-25 7:09 ` Giuseppe CAVALLARO
0 siblings, 1 reply; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-25 2:12 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>> Hello Kelvin.
>>>
>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>
>>> [snip]
>>>
>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>> avoid duplicate code?
>>>
>>> Sorry for my misunderstanding.
>>>
>>> I think you have to use the normal descriptor and remove the enh_desc
>>> from the platform w/o modifying the driver at all.
>>>
>>> The driver will be able to select/configure all automatically (also
>>> jumbo).
>>>
>>> Let me know.
>>
>> That's the problem.
>> The bitfield definition of Loongson1B is also different from normal
>> descriptor.
>
> The problem is not in the Loongson1B gmac.
I found that the bit checksum_insertion is not existed in normal descriptor.
> The normal descriptor fields in the stmmac refer to an old synopsys
> databook.
Could you send me the new databook of Synopsys GMAC?
> New chips have the same structure you have added; so we should fix this
> in the driver w/o breaking the compatibility for old chips.
Agree.
> I kindly ask you to confirm if the currently normal descriptor structure
> (w/o your changes) doesn't work on your platform.
> Did you test it?
Well, the normal descriptor works on my platform except TX checksum offload.
>> Moreover, I want to enable the TX checksum offload function which is
>> not supported in normal descriptor.
>> Any suggestions?
>
> It is supported but you have to pass from the platform: tx_coe = 1.
I noticed that the flag csum_insertion is passed to
ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
just ignores it.
In other words, the TX checksum offload function is disabled in normal
descriptor currently.
Should we fix this problem for normal descriptor?
> Peppe
>>
>>> Note:
>>> IIRC, there is a bit difference in case of normal descriptors for
>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>> In any case, I remember that, on some platforms, the normal descriptors
>>> have been used w/o problems also on these new chip generations.
>>>
>>> Peppe
>>>
>>>
>>
>>
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-25 2:12 ` Kelvin Cheung
@ 2011-10-25 7:09 ` Giuseppe CAVALLARO
2011-10-25 8:20 ` Giuseppe CAVALLARO
2011-10-25 9:18 ` Kelvin Cheung
0 siblings, 2 replies; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-25 7:09 UTC (permalink / raw)
To: Kelvin Cheung
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>> Hello Kelvin.
>>>>
>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>
>>>> [snip]
>>>>
>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>> avoid duplicate code?
>>>>
>>>> Sorry for my misunderstanding.
>>>>
>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>> from the platform w/o modifying the driver at all.
>>>>
>>>> The driver will be able to select/configure all automatically (also
>>>> jumbo).
>>>>
>>>> Let me know.
>>>
>>> That's the problem.
>>> The bitfield definition of Loongson1B is also different from normal
>>> descriptor.
>>
>> The problem is not in the Loongson1B gmac.
>
> I found that the bit checksum_insertion is not existed in normal descriptor.
>
>> The normal descriptor fields in the stmmac refer to an old synopsys
>> databook.
>
> Could you send me the new databook of Synopsys GMAC?
>
>> New chips have the same structure you have added; so we should fix this
>> in the driver w/o breaking the compatibility for old chips.
>
> Agree.
>
>> I kindly ask you to confirm if the currently normal descriptor structure
>> (w/o your changes) doesn't work on your platform.
>> Did you test it?
>
> Well, the normal descriptor works on my platform except TX checksum offload.
ok! I suspected that.
>>> Moreover, I want to enable the TX checksum offload function which is
>>> not supported in normal descriptor.
>>> Any suggestions?
>>
>> It is supported but you have to pass from the platform: tx_coe = 1.
>
> I noticed that the flag csum_insertion is passed to
> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
> just ignores it.
> In other words, the TX checksum offload function is disabled in normal
> descriptor currently.
>
> Should we fix this problem for normal descriptor?
Yes, we should. If you agree, I'll update the normal descriptor
structure to yours. This is the normal descriptor used in newer GMAC.
Tx csum will be done for normal descriptors in case of these GMAC
devices and not for old MAC10/100. For the MAC10/100 some bits for
normal descriptors are reserved and won't be used at all.
I'll also verify that the patch doesn't break the back-compatibility
with old MAC10/100. I have the HW where doing the tests.
After that, I'll prepare the patch for net-next and for your kernel.
>
>> Peppe
>>>
>>>> Note:
>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>> In any case, I remember that, on some platforms, the normal descriptors
>>>> have been used w/o problems also on these new chip generations.
>>>>
>>>> Peppe
>>>>
>>>>
>>>
>>>
>>
>>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-25 7:09 ` Giuseppe CAVALLARO
@ 2011-10-25 8:20 ` Giuseppe CAVALLARO
2011-10-25 9:21 ` Kelvin Cheung
2011-10-26 4:27 ` Kelvin Cheung
2011-10-25 9:18 ` Kelvin Cheung
1 sibling, 2 replies; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-25 8:20 UTC (permalink / raw)
To: Kelvin Cheung
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
[-- Attachment #1: Type: text/plain, Size: 3770 bytes --]
On 10/25/2011 9:09 AM, Giuseppe CAVALLARO wrote:
> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>> Hello Kelvin.
>>>>>
>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>> avoid duplicate code?
>>>>>
>>>>> Sorry for my misunderstanding.
>>>>>
>>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>>> from the platform w/o modifying the driver at all.
>>>>>
>>>>> The driver will be able to select/configure all automatically (also
>>>>> jumbo).
>>>>>
>>>>> Let me know.
>>>>
>>>> That's the problem.
>>>> The bitfield definition of Loongson1B is also different from normal
>>>> descriptor.
>>>
>>> The problem is not in the Loongson1B gmac.
>>
>> I found that the bit checksum_insertion is not existed in normal descriptor.
>>
>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>> databook.
>>
>> Could you send me the new databook of Synopsys GMAC?
>>
>>> New chips have the same structure you have added; so we should fix this
>>> in the driver w/o breaking the compatibility for old chips.
>>
>> Agree.
>>
>>> I kindly ask you to confirm if the currently normal descriptor structure
>>> (w/o your changes) doesn't work on your platform.
>>> Did you test it?
>>
>> Well, the normal descriptor works on my platform except TX checksum offload.
>
> ok! I suspected that.
>
>
>>>> Moreover, I want to enable the TX checksum offload function which is
>>>> not supported in normal descriptor.
>>>> Any suggestions?
>>>
>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>
>> I noticed that the flag csum_insertion is passed to
>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>> just ignores it.
>> In other words, the TX checksum offload function is disabled in normal
>> descriptor currently.
>>
>> Should we fix this problem for normal descriptor?
>
> Yes, we should. If you agree, I'll update the normal descriptor
> structure to yours. This is the normal descriptor used in newer GMAC.
> Tx csum will be done for normal descriptors in case of these GMAC
> devices and not for old MAC10/100. For the MAC10/100 some bits for
> normal descriptors are reserved and won't be used at all.
>
> I'll also verify that the patch doesn't break the back-compatibility
> with old MAC10/100. I have the HW where doing the tests.
>
> After that, I'll prepare the patch for net-next and for your kernel.
Hello Kelvin
attached the patch tested on my development kernel.
It runs fine on old and new mac devices.
Can you try it on your side? Hmm, it is likely it won't apply fine on
your tree but you know the changes ;-).
If ok, I'll rework it for net-next and send it to the mailing list.
Thanks
Peppe
>
>>
>>> Peppe
>>>>
>>>>> Note:
>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>>> In any case, I remember that, on some platforms, the normal descriptors
>>>>> have been used w/o problems also on these new chip generations.
>>>>>
>>>>> Peppe
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
[-- Attachment #2: 0002-stmmac-update-normal-descriptor-structure.patch --]
[-- Type: text/x-patch, Size: 7086 bytes --]
>From 85da9c92eace0b56148e9eedad1061ed72271409 Mon Sep 17 00:00:00 2001
From: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Date: Tue, 25 Oct 2011 09:46:41 +0200
Subject: [PATCH (sh-2.6.32.y) 2/2] stmmac: update normal descriptor structure
This patch updates the normal descriptor structure
to work fine on new GMAC Synopsys chips.
Normal descriptors were designed on the old MAC10/100
databook 1.91 where some bits were reserved: for example
the tx checksum insertion.
The patch maintains the back-compatibility with old
MAC devices (tested on STx7109 MAC10/100) and adds new
fields that actually new GMAC devices can use.
For example, STx7109 will pass from the platform
tx_coe = 0, enh_desc = 0, has_gmac = 0.
A platform like Loongson1B (Mips) will pass:
tx_coe = 1, enh_desc = 0, has_gmac = 1.
Thanks to Kelvin, he enhanced the normal descriptors for
GMAC on Loongson1B.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
drivers/net/stmmac/common.h | 8 ++++----
drivers/net/stmmac/descs.h | 31 ++++++++++++++++++-------------
drivers/net/stmmac/norm_desc.c | 34 ++++++++++++++++++++--------------
drivers/net/stmmac/stmmac_ethtool.c | 8 ++++----
4 files changed, 46 insertions(+), 35 deletions(-)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 9100c10..2cc1192 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -49,7 +49,7 @@ struct stmmac_extra_stats {
unsigned long tx_underflow ____cacheline_aligned;
unsigned long tx_carrier;
unsigned long tx_losscarrier;
- unsigned long tx_heartbeat;
+ unsigned long vlan_tag;
unsigned long tx_deferred;
unsigned long tx_vlan;
unsigned long tx_jabber;
@@ -58,9 +58,9 @@ struct stmmac_extra_stats {
unsigned long tx_ip_header_error;
/* Receive errors */
unsigned long rx_desc;
- unsigned long rx_partial;
- unsigned long rx_runt;
- unsigned long rx_toolong;
+ unsigned long sa_filter_fail;
+ unsigned long overflow_error;
+ unsigned long ipc_csum_error;
unsigned long rx_collision;
unsigned long rx_crc;
unsigned long rx_length;
diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
index 63a03e2..9820ec8 100644
--- a/drivers/net/stmmac/descs.h
+++ b/drivers/net/stmmac/descs.h
@@ -25,33 +25,34 @@ struct dma_desc {
union {
struct {
/* RDES0 */
- u32 reserved1:1;
+ u32 payload_csum_error:1;
u32 crc_error:1;
u32 dribbling:1;
u32 mii_error:1;
u32 receive_watchdog:1;
u32 frame_type:1;
u32 collision:1;
- u32 frame_too_long:1;
+ u32 ipc_csum_error:1;
u32 last_descriptor:1;
u32 first_descriptor:1;
- u32 multicast_frame:1;
- u32 run_frame:1;
+ u32 vlan_tag:1;
+ u32 overflow_error:1;
u32 length_error:1;
- u32 partial_frame_error:1;
+ u32 sa_filter_fail:1;
u32 descriptor_error:1;
u32 error_summary:1;
u32 frame_length:14;
- u32 filtering_fail:1;
+ u32 da_filter_fail:1;
u32 own:1;
/* RDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved2:2;
+ u32 reserved1:2;
u32 second_address_chained:1;
u32 end_ring:1;
- u32 reserved3:5;
+ u32 reserved2:5;
u32 disable_ic:1;
+
} rx;
struct {
/* RDES0 */
@@ -91,24 +92,28 @@ struct dma_desc {
u32 underflow_error:1;
u32 excessive_deferral:1;
u32 collision_count:4;
- u32 heartbeat_fail:1;
+ u32 vlan_frame:1;
u32 excessive_collisions:1;
u32 late_collision:1;
u32 no_carrier:1;
u32 loss_carrier:1;
- u32 reserved1:3;
+ u32 payload_error:1;
+ u32 frame_flushed:1;
+ u32 jabber_timeout:1;
u32 error_summary:1;
- u32 reserved2:15;
+ u32 ip_header_error:1;
+ u32 time_stamp_status:1;
+ u32 reserved1:13;
u32 own:1;
/* TDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved3:1;
+ u32 time_stamp_enable:1;
u32 disable_padding:1;
u32 second_address_chained:1;
u32 end_ring:1;
u32 crc_disable:1;
- u32 reserved4:2;
+ u32 checksum_insertion:2;
u32 first_segment:1;
u32 last_segment:1;
u32 interrupt:1;
diff --git a/drivers/net/stmmac/norm_desc.c b/drivers/net/stmmac/norm_desc.c
index f7e8ba7..c7c1522 100644
--- a/drivers/net/stmmac/norm_desc.c
+++ b/drivers/net/stmmac/norm_desc.c
@@ -50,11 +50,12 @@ static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
stats->collisions += p->des01.tx.collision_count;
ret = -1;
}
- if (unlikely(p->des01.tx.heartbeat_fail)) {
- x->tx_heartbeat++;
- stats->tx_heartbeat_errors++;
- ret = -1;
- }
+
+ if (p->des01.etx.vlan_frame) {
+ CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
+ x->tx_vlan++;
+ }
+
if (unlikely(p->des01.tx.deferred))
x->tx_deferred++;
@@ -86,12 +87,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.rx.error_summary)) {
if (unlikely(p->des01.rx.descriptor_error))
x->rx_desc++;
- if (unlikely(p->des01.rx.partial_frame_error))
- x->rx_partial++;
- if (unlikely(p->des01.rx.run_frame))
- x->rx_runt++;
- if (unlikely(p->des01.rx.frame_too_long))
- x->rx_toolong++;
+ if (unlikely(p->des01.rx.sa_filter_fail))
+ x->sa_filter_fail++;
+ if (unlikely(p->des01.rx.overflow_error))
+ x->overflow_error++;
+ if (unlikely(p->des01.rx.ipc_csum_error))
+ x->ipc_csum_error++;
if (unlikely(p->des01.rx.collision)) {
x->rx_collision++;
stats->collisions++;
@@ -113,10 +114,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
x->rx_mii++;
ret = discard_frame;
}
- if (p->des01.rx.multicast_frame) {
- x->rx_multicast++;
- stats->multicast++;
+#ifdef STMMAC_VLAN_TAG_USED
+ if (p->des01.rx.vlan_tag) {
+ x->vlan_tag++;
+ stats->vlan_tag++;
}
+#endif
return ret;
}
@@ -184,6 +187,9 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
{
p->des01.tx.first_segment = is_fs;
norm_set_tx_desc_len(p, len);
+
+ if (likely(csum_flag))
+ p->des01.tx.checksum_insertion = cic_full;
}
static void ndesc_clear_tx_ic(struct dma_desc *p)
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index d81cf20..6831cf2 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -48,7 +48,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_underflow),
STMMAC_STAT(tx_carrier),
STMMAC_STAT(tx_losscarrier),
- STMMAC_STAT(tx_heartbeat),
+ STMMAC_STAT(vlan_tag),
STMMAC_STAT(tx_deferred),
STMMAC_STAT(tx_vlan),
STMMAC_STAT(rx_vlan),
@@ -57,9 +57,9 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_payload_error),
STMMAC_STAT(tx_ip_header_error),
STMMAC_STAT(rx_desc),
- STMMAC_STAT(rx_partial),
- STMMAC_STAT(rx_runt),
- STMMAC_STAT(rx_toolong),
+ STMMAC_STAT(sa_filter_fail),
+ STMMAC_STAT(overflow_error),
+ STMMAC_STAT(ipc_csum_error),
STMMAC_STAT(rx_collision),
STMMAC_STAT(rx_crc),
STMMAC_STAT(rx_length),
--
1.7.4.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-25 7:09 ` Giuseppe CAVALLARO
2011-10-25 8:20 ` Giuseppe CAVALLARO
@ 2011-10-25 9:18 ` Kelvin Cheung
1 sibling, 0 replies; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-25 9:18 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
2011/10/25, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>> Hello Kelvin.
>>>>>
>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>> avoid duplicate code?
>>>>>
>>>>> Sorry for my misunderstanding.
>>>>>
>>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>>> from the platform w/o modifying the driver at all.
>>>>>
>>>>> The driver will be able to select/configure all automatically (also
>>>>> jumbo).
>>>>>
>>>>> Let me know.
>>>>
>>>> That's the problem.
>>>> The bitfield definition of Loongson1B is also different from normal
>>>> descriptor.
>>>
>>> The problem is not in the Loongson1B gmac.
>>
>> I found that the bit checksum_insertion is not existed in normal
>> descriptor.
>>
>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>> databook.
>>
>> Could you send me the new databook of Synopsys GMAC?
>>
>>> New chips have the same structure you have added; so we should fix this
>>> in the driver w/o breaking the compatibility for old chips.
>>
>> Agree.
>>
>>> I kindly ask you to confirm if the currently normal descriptor structure
>>> (w/o your changes) doesn't work on your platform.
>>> Did you test it?
>>
>> Well, the normal descriptor works on my platform except TX checksum
>> offload.
>
> ok! I suspected that.
>
>
>>>> Moreover, I want to enable the TX checksum offload function which is
>>>> not supported in normal descriptor.
>>>> Any suggestions?
>>>
>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>
>> I noticed that the flag csum_insertion is passed to
>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>> just ignores it.
>> In other words, the TX checksum offload function is disabled in normal
>> descriptor currently.
>>
>> Should we fix this problem for normal descriptor?
>
> Yes, we should. If you agree, I'll update the normal descriptor
> structure to yours. This is the normal descriptor used in newer GMAC.
> Tx csum will be done for normal descriptors in case of these GMAC
> devices and not for old MAC10/100. For the MAC10/100 some bits for
> normal descriptors are reserved and won't be used at all.
Fully agree.
> I'll also verify that the patch doesn't break the back-compatibility
> with old MAC10/100. I have the HW where doing the tests.
>
> After that, I'll prepare the patch for net-next and for your kernel.
Thanks!
>>
>>> Peppe
>>>>
>>>>> Note:
>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>>> In any case, I remember that, on some platforms, the normal descriptors
>>>>> have been used w/o problems also on these new chip generations.
>>>>>
>>>>> Peppe
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>
>>
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-25 8:20 ` Giuseppe CAVALLARO
@ 2011-10-25 9:21 ` Kelvin Cheung
2011-10-26 4:27 ` Kelvin Cheung
1 sibling, 0 replies; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-25 9:21 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
2011/10/25, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> On 10/25/2011 9:09 AM, Giuseppe CAVALLARO wrote:
>> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>>> Hello Kelvin.
>>>>>>
>>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>>
>>>>>> [snip]
>>>>>>
>>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>>> avoid duplicate code?
>>>>>>
>>>>>> Sorry for my misunderstanding.
>>>>>>
>>>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>>>> from the platform w/o modifying the driver at all.
>>>>>>
>>>>>> The driver will be able to select/configure all automatically (also
>>>>>> jumbo).
>>>>>>
>>>>>> Let me know.
>>>>>
>>>>> That's the problem.
>>>>> The bitfield definition of Loongson1B is also different from normal
>>>>> descriptor.
>>>>
>>>> The problem is not in the Loongson1B gmac.
>>>
>>> I found that the bit checksum_insertion is not existed in normal
>>> descriptor.
>>>
>>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>>> databook.
>>>
>>> Could you send me the new databook of Synopsys GMAC?
>>>
>>>> New chips have the same structure you have added; so we should fix this
>>>> in the driver w/o breaking the compatibility for old chips.
>>>
>>> Agree.
>>>
>>>> I kindly ask you to confirm if the currently normal descriptor structure
>>>> (w/o your changes) doesn't work on your platform.
>>>> Did you test it?
>>>
>>> Well, the normal descriptor works on my platform except TX checksum
>>> offload.
>>
>> ok! I suspected that.
>>
>>
>>>>> Moreover, I want to enable the TX checksum offload function which is
>>>>> not supported in normal descriptor.
>>>>> Any suggestions?
>>>>
>>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>>
>>> I noticed that the flag csum_insertion is passed to
>>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>>> just ignores it.
>>> In other words, the TX checksum offload function is disabled in normal
>>> descriptor currently.
>>>
>>> Should we fix this problem for normal descriptor?
>>
>> Yes, we should. If you agree, I'll update the normal descriptor
>> structure to yours. This is the normal descriptor used in newer GMAC.
>> Tx csum will be done for normal descriptors in case of these GMAC
>> devices and not for old MAC10/100. For the MAC10/100 some bits for
>> normal descriptors are reserved and won't be used at all.
>>
>> I'll also verify that the patch doesn't break the back-compatibility
>> with old MAC10/100. I have the HW where doing the tests.
>>
>> After that, I'll prepare the patch for net-next and for your kernel.
>
> Hello Kelvin
>
> attached the patch tested on my development kernel.
> It runs fine on old and new mac devices.
>
> Can you try it on your side? Hmm, it is likely it won't apply fine on
> your tree but you know the changes ;-).
Sure.
> If ok, I'll rework it for net-next and send it to the mailing list.
>
> Thanks
> Peppe
>
>>
>>>
>>>> Peppe
>>>>>
>>>>>> Note:
>>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>>>> In any case, I remember that, on some platforms, the normal
>>>>>> descriptors
>>>>>> have been used w/o problems also on these new chip generations.
>>>>>>
>>>>>> Peppe
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-25 8:20 ` Giuseppe CAVALLARO
2011-10-25 9:21 ` Kelvin Cheung
@ 2011-10-26 4:27 ` Kelvin Cheung
2011-10-26 7:20 ` Giuseppe CAVALLARO
1 sibling, 1 reply; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-26 4:27 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
[-- Attachment #1: Type: text/plain, Size: 4272 bytes --]
Hi Giuseppe,
This patch works well on Loongson1B platform except one thing.
The rx checksum offload of normal descriptor is disabled by default.
So, I enabled this functon. And one minor tweak is added to your patch.
What about your opinion?
BTW, tx checksum insertion works now.
2011/10/25, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> On 10/25/2011 9:09 AM, Giuseppe CAVALLARO wrote:
>> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>>> Hello Kelvin.
>>>>>>
>>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>>
>>>>>> [snip]
>>>>>>
>>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>>> avoid duplicate code?
>>>>>>
>>>>>> Sorry for my misunderstanding.
>>>>>>
>>>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>>>> from the platform w/o modifying the driver at all.
>>>>>>
>>>>>> The driver will be able to select/configure all automatically (also
>>>>>> jumbo).
>>>>>>
>>>>>> Let me know.
>>>>>
>>>>> That's the problem.
>>>>> The bitfield definition of Loongson1B is also different from normal
>>>>> descriptor.
>>>>
>>>> The problem is not in the Loongson1B gmac.
>>>
>>> I found that the bit checksum_insertion is not existed in normal
>>> descriptor.
>>>
>>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>>> databook.
>>>
>>> Could you send me the new databook of Synopsys GMAC?
>>>
>>>> New chips have the same structure you have added; so we should fix this
>>>> in the driver w/o breaking the compatibility for old chips.
>>>
>>> Agree.
>>>
>>>> I kindly ask you to confirm if the currently normal descriptor structure
>>>> (w/o your changes) doesn't work on your platform.
>>>> Did you test it?
>>>
>>> Well, the normal descriptor works on my platform except TX checksum
>>> offload.
>>
>> ok! I suspected that.
>>
>>
>>>>> Moreover, I want to enable the TX checksum offload function which is
>>>>> not supported in normal descriptor.
>>>>> Any suggestions?
>>>>
>>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>>
>>> I noticed that the flag csum_insertion is passed to
>>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>>> just ignores it.
>>> In other words, the TX checksum offload function is disabled in normal
>>> descriptor currently.
>>>
>>> Should we fix this problem for normal descriptor?
>>
>> Yes, we should. If you agree, I'll update the normal descriptor
>> structure to yours. This is the normal descriptor used in newer GMAC.
>> Tx csum will be done for normal descriptors in case of these GMAC
>> devices and not for old MAC10/100. For the MAC10/100 some bits for
>> normal descriptors are reserved and won't be used at all.
>>
>> I'll also verify that the patch doesn't break the back-compatibility
>> with old MAC10/100. I have the HW where doing the tests.
>>
>> After that, I'll prepare the patch for net-next and for your kernel.
>
> Hello Kelvin
>
> attached the patch tested on my development kernel.
> It runs fine on old and new mac devices.
>
> Can you try it on your side? Hmm, it is likely it won't apply fine on
> your tree but you know the changes ;-).
>
> If ok, I'll rework it for net-next and send it to the mailing list.
>
> Thanks
> Peppe
>
>>
>>>
>>>> Peppe
>>>>>
>>>>>> Note:
>>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>>>> In any case, I remember that, on some platforms, the normal
>>>>>> descriptors
>>>>>> have been used w/o problems also on these new chip generations.
>>>>>>
>>>>>> Peppe
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
--
Best Regards!
Kelvin
[-- Attachment #2: 0001-stmmac-update-normal-descriptor-structure.patch --]
[-- Type: text/x-patch, Size: 7719 bytes --]
From 93ee3effbde61013a886d579fc89c36ddddb35a4 Mon Sep 17 00:00:00 2001
From: Kelvin Cheung <keguang.zhang@gmail.com>
Date: Wed, 26 Oct 2011 11:08:01 +0800
Subject: [PATCH] stmmac: update normal descriptor structure
This patch updates the normal descriptor structure
to work fine on new GMAC Synopsys chips.
Normal descriptors were designed on the old MAC10/100
databook 1.91 where some bits were reserved: for example
the tx checksum insertion and rx checksum offload.
The patch maintains the back-compatibility with old
MAC devices (tested on STx7109 MAC10/100) and adds new
fields that actually new GMAC devices can use.
For example, STx7109 will pass from the platform
tx_coe = 0, enh_desc = 0, has_gmac = 0.
A platform like Loongson1B (Mips) will pass:
tx_coe = 1, enh_desc = 0, has_gmac = 1.
Thanks to Kelvin, he enhanced the normal descriptors for
GMAC on Loongson1B.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
drivers/net/stmmac/common.h | 8 +++---
drivers/net/stmmac/descs.h | 31 +++++++++++++++-----------
drivers/net/stmmac/norm_desc.c | 40 +++++++++++++++++++---------------
drivers/net/stmmac/stmmac_ethtool.c | 8 +++---
4 files changed, 48 insertions(+), 39 deletions(-)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 375ea19..6ec4a8c 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -48,7 +48,7 @@ struct stmmac_extra_stats {
unsigned long tx_underflow ____cacheline_aligned;
unsigned long tx_carrier;
unsigned long tx_losscarrier;
- unsigned long tx_heartbeat;
+ unsigned long vlan_tag;
unsigned long tx_deferred;
unsigned long tx_vlan;
unsigned long tx_jabber;
@@ -57,9 +57,9 @@ struct stmmac_extra_stats {
unsigned long tx_ip_header_error;
/* Receive errors */
unsigned long rx_desc;
- unsigned long rx_partial;
- unsigned long rx_runt;
- unsigned long rx_toolong;
+ unsigned long sa_filter_fail;
+ unsigned long overflow_error;
+ unsigned long ipc_csum_error;
unsigned long rx_collision;
unsigned long rx_crc;
unsigned long rx_length;
diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
index 63a03e2..9820ec8 100644
--- a/drivers/net/stmmac/descs.h
+++ b/drivers/net/stmmac/descs.h
@@ -25,33 +25,34 @@ struct dma_desc {
union {
struct {
/* RDES0 */
- u32 reserved1:1;
+ u32 payload_csum_error:1;
u32 crc_error:1;
u32 dribbling:1;
u32 mii_error:1;
u32 receive_watchdog:1;
u32 frame_type:1;
u32 collision:1;
- u32 frame_too_long:1;
+ u32 ipc_csum_error:1;
u32 last_descriptor:1;
u32 first_descriptor:1;
- u32 multicast_frame:1;
- u32 run_frame:1;
+ u32 vlan_tag:1;
+ u32 overflow_error:1;
u32 length_error:1;
- u32 partial_frame_error:1;
+ u32 sa_filter_fail:1;
u32 descriptor_error:1;
u32 error_summary:1;
u32 frame_length:14;
- u32 filtering_fail:1;
+ u32 da_filter_fail:1;
u32 own:1;
/* RDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved2:2;
+ u32 reserved1:2;
u32 second_address_chained:1;
u32 end_ring:1;
- u32 reserved3:5;
+ u32 reserved2:5;
u32 disable_ic:1;
+
} rx;
struct {
/* RDES0 */
@@ -91,24 +92,28 @@ struct dma_desc {
u32 underflow_error:1;
u32 excessive_deferral:1;
u32 collision_count:4;
- u32 heartbeat_fail:1;
+ u32 vlan_frame:1;
u32 excessive_collisions:1;
u32 late_collision:1;
u32 no_carrier:1;
u32 loss_carrier:1;
- u32 reserved1:3;
+ u32 payload_error:1;
+ u32 frame_flushed:1;
+ u32 jabber_timeout:1;
u32 error_summary:1;
- u32 reserved2:15;
+ u32 ip_header_error:1;
+ u32 time_stamp_status:1;
+ u32 reserved1:13;
u32 own:1;
/* TDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved3:1;
+ u32 time_stamp_enable:1;
u32 disable_padding:1;
u32 second_address_chained:1;
u32 end_ring:1;
u32 crc_disable:1;
- u32 reserved4:2;
+ u32 checksum_insertion:2;
u32 first_segment:1;
u32 last_segment:1;
u32 interrupt:1;
diff --git a/drivers/net/stmmac/norm_desc.c b/drivers/net/stmmac/norm_desc.c
index 7008c29..fab8f0c 100644
--- a/drivers/net/stmmac/norm_desc.c
+++ b/drivers/net/stmmac/norm_desc.c
@@ -49,11 +49,12 @@ static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
stats->collisions += p->des01.tx.collision_count;
ret = -1;
}
- if (unlikely(p->des01.tx.heartbeat_fail)) {
- x->tx_heartbeat++;
- stats->tx_heartbeat_errors++;
- ret = -1;
- }
+
+ if (p->des01.etx.vlan_frame) {
+ CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
+ x->tx_vlan++;
+ }
+
if (unlikely(p->des01.tx.deferred))
x->tx_deferred++;
@@ -66,13 +67,11 @@ static int ndesc_get_tx_len(struct dma_desc *p)
}
/* This function verifies if each incoming frame has some errors
- * and, if required, updates the multicast statistics.
- * In case of success, it returns csum_none because the device
- * is not able to compute the csum in HW. */
+ * and, if required, updates the multicast statistics. */
static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
struct dma_desc *p)
{
- int ret = csum_none;
+ int ret = good_frame;
struct net_device_stats *stats = (struct net_device_stats *)data;
if (unlikely(p->des01.rx.last_descriptor == 0)) {
@@ -85,12 +84,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.rx.error_summary)) {
if (unlikely(p->des01.rx.descriptor_error))
x->rx_desc++;
- if (unlikely(p->des01.rx.partial_frame_error))
- x->rx_partial++;
- if (unlikely(p->des01.rx.run_frame))
- x->rx_runt++;
- if (unlikely(p->des01.rx.frame_too_long))
- x->rx_toolong++;
+ if (unlikely(p->des01.rx.sa_filter_fail))
+ x->sa_filter_fail++;
+ if (unlikely(p->des01.rx.overflow_error))
+ x->overflow_error++;
+ if (unlikely(p->des01.rx.ipc_csum_error))
+ x->ipc_csum_error++;
if (unlikely(p->des01.rx.collision)) {
x->rx_collision++;
stats->collisions++;
@@ -112,10 +111,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
x->rx_mii++;
ret = discard_frame;
}
- if (p->des01.rx.multicast_frame) {
- x->rx_multicast++;
- stats->multicast++;
+#ifdef STMMAC_VLAN_TAG_USED
+ if (p->des01.rx.vlan_tag) {
+ x->vlan_tag++;
+ stats->vlan_tag++;
}
+#endif
return ret;
}
@@ -184,6 +185,9 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
{
p->des01.tx.first_segment = is_fs;
norm_set_tx_desc_len(p, len);
+
+ if (likely(csum_flag))
+ p->des01.tx.checksum_insertion = cic_full;
}
static void ndesc_clear_tx_ic(struct dma_desc *p)
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index 7ed8fb6..3d58fcc 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -50,7 +50,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_underflow),
STMMAC_STAT(tx_carrier),
STMMAC_STAT(tx_losscarrier),
- STMMAC_STAT(tx_heartbeat),
+ STMMAC_STAT(vlan_tag),
STMMAC_STAT(tx_deferred),
STMMAC_STAT(tx_vlan),
STMMAC_STAT(rx_vlan),
@@ -59,9 +59,9 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_payload_error),
STMMAC_STAT(tx_ip_header_error),
STMMAC_STAT(rx_desc),
- STMMAC_STAT(rx_partial),
- STMMAC_STAT(rx_runt),
- STMMAC_STAT(rx_toolong),
+ STMMAC_STAT(sa_filter_fail),
+ STMMAC_STAT(overflow_error),
+ STMMAC_STAT(ipc_csum_error),
STMMAC_STAT(rx_collision),
STMMAC_STAT(rx_crc),
STMMAC_STAT(rx_length),
--
1.7.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-26 4:27 ` Kelvin Cheung
@ 2011-10-26 7:20 ` Giuseppe CAVALLARO
2011-10-26 7:48 ` Kelvin Cheung
0 siblings, 1 reply; 19+ messages in thread
From: Giuseppe CAVALLARO @ 2011-10-26 7:20 UTC (permalink / raw)
To: Kelvin Cheung
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
[-- Attachment #1: Type: text/plain, Size: 4725 bytes --]
Hello Kelvin
On 10/26/2011 6:27 AM, Kelvin Cheung wrote:
> Hi Giuseppe,
>
> This patch works well on Loongson1B platform except one thing.
> The rx checksum offload of normal descriptor is disabled by default.
> So, I enabled this functon. And one minor tweak is added to your patch.
> What about your opinion?
Yes, I had not enabled the rx coe. I'm resending your patch (v3) where I
fixed a problem. Old mac10/100 has no rx csum in HW. So I added an extra
check.
Let me consider it the final version. ;-)
Thanks a lot for you effort.
I'll send it for net-next now.
Regards
Peppe
>
> BTW, tx checksum insertion works now.
>
> 2011/10/25, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>> On 10/25/2011 9:09 AM, Giuseppe CAVALLARO wrote:
>>> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>>>> Hello Kelvin.
>>>>>>>
>>>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>>>
>>>>>>> [snip]
>>>>>>>
>>>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>>>> avoid duplicate code?
>>>>>>>
>>>>>>> Sorry for my misunderstanding.
>>>>>>>
>>>>>>> I think you have to use the normal descriptor and remove the enh_desc
>>>>>>> from the platform w/o modifying the driver at all.
>>>>>>>
>>>>>>> The driver will be able to select/configure all automatically (also
>>>>>>> jumbo).
>>>>>>>
>>>>>>> Let me know.
>>>>>>
>>>>>> That's the problem.
>>>>>> The bitfield definition of Loongson1B is also different from normal
>>>>>> descriptor.
>>>>>
>>>>> The problem is not in the Loongson1B gmac.
>>>>
>>>> I found that the bit checksum_insertion is not existed in normal
>>>> descriptor.
>>>>
>>>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>>>> databook.
>>>>
>>>> Could you send me the new databook of Synopsys GMAC?
>>>>
>>>>> New chips have the same structure you have added; so we should fix this
>>>>> in the driver w/o breaking the compatibility for old chips.
>>>>
>>>> Agree.
>>>>
>>>>> I kindly ask you to confirm if the currently normal descriptor structure
>>>>> (w/o your changes) doesn't work on your platform.
>>>>> Did you test it?
>>>>
>>>> Well, the normal descriptor works on my platform except TX checksum
>>>> offload.
>>>
>>> ok! I suspected that.
>>>
>>>
>>>>>> Moreover, I want to enable the TX checksum offload function which is
>>>>>> not supported in normal descriptor.
>>>>>> Any suggestions?
>>>>>
>>>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>>>
>>>> I noticed that the flag csum_insertion is passed to
>>>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>>>> just ignores it.
>>>> In other words, the TX checksum offload function is disabled in normal
>>>> descriptor currently.
>>>>
>>>> Should we fix this problem for normal descriptor?
>>>
>>> Yes, we should. If you agree, I'll update the normal descriptor
>>> structure to yours. This is the normal descriptor used in newer GMAC.
>>> Tx csum will be done for normal descriptors in case of these GMAC
>>> devices and not for old MAC10/100. For the MAC10/100 some bits for
>>> normal descriptors are reserved and won't be used at all.
>>>
>>> I'll also verify that the patch doesn't break the back-compatibility
>>> with old MAC10/100. I have the HW where doing the tests.
>>>
>>> After that, I'll prepare the patch for net-next and for your kernel.
>>
>> Hello Kelvin
>>
>> attached the patch tested on my development kernel.
>> It runs fine on old and new mac devices.
>>
>> Can you try it on your side? Hmm, it is likely it won't apply fine on
>> your tree but you know the changes ;-).
>>
>> If ok, I'll rework it for net-next and send it to the mailing list.
>>
>> Thanks
>> Peppe
>>
>>>
>>>>
>>>>> Peppe
>>>>>>
>>>>>>> Note:
>>>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>>>> Synopsys databook newer than the 1.91 (I used for testing this mode).
>>>>>>> In any case, I remember that, on some platforms, the normal
>>>>>>> descriptors
>>>>>>> have been used w/o problems also on these new chip generations.
>>>>>>>
>>>>>>> Peppe
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>
>>
>>
>
>
[-- Attachment #2: 0001-stmmac-update-normal-descriptor-structure-v3.patch --]
[-- Type: text/x-patch, Size: 8441 bytes --]
>From 324c8e56e728046590bae14d14e8ff09978b71b4 Mon Sep 17 00:00:00 2001
From: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Date: Tue, 25 Oct 2011 09:46:41 +0200
Subject: [PATCH (sh-2.6.32.y)] stmmac: update normal descriptor structure
(v3)
This patch updates the normal descriptor structure
to work fine on new GMAC Synopsys chips.
Normal descriptors were designed on the old MAC10/100
databook 1.91 where some bits were reserved: for example
the tx checksum insertion and rx checksum offload.
The patch maintains the back-compatibility with old
MAC devices (tested on STx7109 MAC10/100) and adds new
fields that actually new GMAC devices can use.
For example, STx7109 will pass from the platform
tx_coe = 0, enh_desc = 0, has_gmac = 0.
A platform like Loongson1B (Mips) will pass:
tx_coe = 1, enh_desc = 0, has_gmac = 1.
Thanks to Kelvin, he enhanced the normal descriptors for
GMAC on Loongson1B.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
drivers/net/stmmac/common.h | 8 +++---
drivers/net/stmmac/descs.h | 31 +++++++++++++++-----------
drivers/net/stmmac/norm_desc.c | 40 ++++++++++++++++++++--------------
drivers/net/stmmac/stmmac_ethtool.c | 8 +++---
drivers/net/stmmac/stmmac_main.c | 4 +-
5 files changed, 51 insertions(+), 40 deletions(-)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 9100c10..2cc1192 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -49,7 +49,7 @@ struct stmmac_extra_stats {
unsigned long tx_underflow ____cacheline_aligned;
unsigned long tx_carrier;
unsigned long tx_losscarrier;
- unsigned long tx_heartbeat;
+ unsigned long vlan_tag;
unsigned long tx_deferred;
unsigned long tx_vlan;
unsigned long tx_jabber;
@@ -58,9 +58,9 @@ struct stmmac_extra_stats {
unsigned long tx_ip_header_error;
/* Receive errors */
unsigned long rx_desc;
- unsigned long rx_partial;
- unsigned long rx_runt;
- unsigned long rx_toolong;
+ unsigned long sa_filter_fail;
+ unsigned long overflow_error;
+ unsigned long ipc_csum_error;
unsigned long rx_collision;
unsigned long rx_crc;
unsigned long rx_length;
diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
index 63a03e2..9820ec8 100644
--- a/drivers/net/stmmac/descs.h
+++ b/drivers/net/stmmac/descs.h
@@ -25,33 +25,34 @@ struct dma_desc {
union {
struct {
/* RDES0 */
- u32 reserved1:1;
+ u32 payload_csum_error:1;
u32 crc_error:1;
u32 dribbling:1;
u32 mii_error:1;
u32 receive_watchdog:1;
u32 frame_type:1;
u32 collision:1;
- u32 frame_too_long:1;
+ u32 ipc_csum_error:1;
u32 last_descriptor:1;
u32 first_descriptor:1;
- u32 multicast_frame:1;
- u32 run_frame:1;
+ u32 vlan_tag:1;
+ u32 overflow_error:1;
u32 length_error:1;
- u32 partial_frame_error:1;
+ u32 sa_filter_fail:1;
u32 descriptor_error:1;
u32 error_summary:1;
u32 frame_length:14;
- u32 filtering_fail:1;
+ u32 da_filter_fail:1;
u32 own:1;
/* RDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved2:2;
+ u32 reserved1:2;
u32 second_address_chained:1;
u32 end_ring:1;
- u32 reserved3:5;
+ u32 reserved2:5;
u32 disable_ic:1;
+
} rx;
struct {
/* RDES0 */
@@ -91,24 +92,28 @@ struct dma_desc {
u32 underflow_error:1;
u32 excessive_deferral:1;
u32 collision_count:4;
- u32 heartbeat_fail:1;
+ u32 vlan_frame:1;
u32 excessive_collisions:1;
u32 late_collision:1;
u32 no_carrier:1;
u32 loss_carrier:1;
- u32 reserved1:3;
+ u32 payload_error:1;
+ u32 frame_flushed:1;
+ u32 jabber_timeout:1;
u32 error_summary:1;
- u32 reserved2:15;
+ u32 ip_header_error:1;
+ u32 time_stamp_status:1;
+ u32 reserved1:13;
u32 own:1;
/* TDES1 */
u32 buffer1_size:11;
u32 buffer2_size:11;
- u32 reserved3:1;
+ u32 time_stamp_enable:1;
u32 disable_padding:1;
u32 second_address_chained:1;
u32 end_ring:1;
u32 crc_disable:1;
- u32 reserved4:2;
+ u32 checksum_insertion:2;
u32 first_segment:1;
u32 last_segment:1;
u32 interrupt:1;
diff --git a/drivers/net/stmmac/norm_desc.c b/drivers/net/stmmac/norm_desc.c
index f7e8ba7..3955ae7 100644
--- a/drivers/net/stmmac/norm_desc.c
+++ b/drivers/net/stmmac/norm_desc.c
@@ -50,11 +50,12 @@ static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
stats->collisions += p->des01.tx.collision_count;
ret = -1;
}
- if (unlikely(p->des01.tx.heartbeat_fail)) {
- x->tx_heartbeat++;
- stats->tx_heartbeat_errors++;
- ret = -1;
- }
+
+ if (p->des01.etx.vlan_frame) {
+ CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
+ x->tx_vlan++;
+ }
+
if (unlikely(p->des01.tx.deferred))
x->tx_deferred++;
@@ -68,12 +69,12 @@ static int ndesc_get_tx_len(struct dma_desc *p)
/* This function verifies if each incoming frame has some errors
* and, if required, updates the multicast statistics.
- * In case of success, it returns csum_none because the device
- * is not able to compute the csum in HW. */
+ * In case of success, it returns good_frame because the GMAC device
+ * is supposed to be able to compute the csum in HW. */
static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
struct dma_desc *p)
{
- int ret = csum_none;
+ int ret = good_frame;
struct net_device_stats *stats = (struct net_device_stats *)data;
if (unlikely(p->des01.rx.last_descriptor == 0)) {
@@ -86,12 +87,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.rx.error_summary)) {
if (unlikely(p->des01.rx.descriptor_error))
x->rx_desc++;
- if (unlikely(p->des01.rx.partial_frame_error))
- x->rx_partial++;
- if (unlikely(p->des01.rx.run_frame))
- x->rx_runt++;
- if (unlikely(p->des01.rx.frame_too_long))
- x->rx_toolong++;
+ if (unlikely(p->des01.rx.sa_filter_fail))
+ x->sa_filter_fail++;
+ if (unlikely(p->des01.rx.overflow_error))
+ x->overflow_error++;
+ if (unlikely(p->des01.rx.ipc_csum_error))
+ x->ipc_csum_error++;
if (unlikely(p->des01.rx.collision)) {
x->rx_collision++;
stats->collisions++;
@@ -113,10 +114,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
x->rx_mii++;
ret = discard_frame;
}
- if (p->des01.rx.multicast_frame) {
- x->rx_multicast++;
- stats->multicast++;
+#ifdef STMMAC_VLAN_TAG_USED
+ if (p->des01.rx.vlan_tag) {
+ x->vlan_tag++;
+ stats->vlan_tag++;
}
+#endif
return ret;
}
@@ -184,6 +187,9 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
{
p->des01.tx.first_segment = is_fs;
norm_set_tx_desc_len(p, len);
+
+ if (likely(csum_flag))
+ p->des01.tx.checksum_insertion = cic_full;
}
static void ndesc_clear_tx_ic(struct dma_desc *p)
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index d81cf20..6831cf2 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -48,7 +48,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_underflow),
STMMAC_STAT(tx_carrier),
STMMAC_STAT(tx_losscarrier),
- STMMAC_STAT(tx_heartbeat),
+ STMMAC_STAT(vlan_tag),
STMMAC_STAT(tx_deferred),
STMMAC_STAT(tx_vlan),
STMMAC_STAT(rx_vlan),
@@ -57,9 +57,9 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
STMMAC_STAT(tx_payload_error),
STMMAC_STAT(tx_ip_header_error),
STMMAC_STAT(rx_desc),
- STMMAC_STAT(rx_partial),
- STMMAC_STAT(rx_runt),
- STMMAC_STAT(rx_toolong),
+ STMMAC_STAT(sa_filter_fail),
+ STMMAC_STAT(overflow_error),
+ STMMAC_STAT(ipc_csum_error),
STMMAC_STAT(rx_collision),
STMMAC_STAT(rx_crc),
STMMAC_STAT(rx_length),
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 3a3efb1..18e614b 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1318,8 +1318,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
#endif
skb->protocol = eth_type_trans(skb, priv->dev);
- if (unlikely(status == csum_none)) {
- /* always for the old mac 10/100 */
+ if (unlikely(!priv->plat->has_gmac)) {
+ /* No csum for the old mac 10/100 devices */
skb->ip_summed = CHECKSUM_NONE;
netif_receive_skb(skb);
} else {
--
1.7.4.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-26 7:20 ` Giuseppe CAVALLARO
@ 2011-10-26 7:48 ` Kelvin Cheung
0 siblings, 0 replies; 19+ messages in thread
From: Kelvin Cheung @ 2011-10-26 7:48 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: Wu Zhangjin, linux-mips, linux-kernel, ralf, r0bertz, netdev
It's perfect now.
Please add me to CC list when you send the new patch.
Thanks a lot for your help.
2011/10/26, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
> Hello Kelvin
>
> On 10/26/2011 6:27 AM, Kelvin Cheung wrote:
>> Hi Giuseppe,
>>
>> This patch works well on Loongson1B platform except one thing.
>> The rx checksum offload of normal descriptor is disabled by default.
>> So, I enabled this functon. And one minor tweak is added to your patch.
>> What about your opinion?
>
> Yes, I had not enabled the rx coe. I'm resending your patch (v3) where I
> fixed a problem. Old mac10/100 has no rx csum in HW. So I added an extra
> check.
> Let me consider it the final version. ;-)
>
> Thanks a lot for you effort.
> I'll send it for net-next now.
>
> Regards
> Peppe
>
>>
>> BTW, tx checksum insertion works now.
>>
>> 2011/10/25, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>> On 10/25/2011 9:09 AM, Giuseppe CAVALLARO wrote:
>>>> On 10/25/2011 4:12 AM, Kelvin Cheung wrote:
>>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>>> On 10/24/2011 4:05 PM, Kelvin Cheung wrote:
>>>>>>> 2011/10/24, Giuseppe CAVALLARO <peppe.cavallaro@st.com>:
>>>>>>>> Hello Kelvin.
>>>>>>>>
>>>>>>>> On 10/24/2011 12:36 PM, Kelvin Cheung wrote:
>>>>>>>>
>>>>>>>> [snip]
>>>>>>>>
>>>>>>>>> According to datasheet of Loongson 1B, the buffer size in RX/TX
>>>>>>>>> descriptor is only 2KB. So the Loongson1B's GMAC could not handle
>>>>>>>>> jumbo frames. And the second buffer is useless in this case. Am I
>>>>>>>>> right? Is there a better way than ifdef CONFIG_MACH_LOONGSON1 to
>>>>>>>>> avoid duplicate code?
>>>>>>>>
>>>>>>>> Sorry for my misunderstanding.
>>>>>>>>
>>>>>>>> I think you have to use the normal descriptor and remove the
>>>>>>>> enh_desc
>>>>>>>> from the platform w/o modifying the driver at all.
>>>>>>>>
>>>>>>>> The driver will be able to select/configure all automatically (also
>>>>>>>> jumbo).
>>>>>>>>
>>>>>>>> Let me know.
>>>>>>>
>>>>>>> That's the problem.
>>>>>>> The bitfield definition of Loongson1B is also different from normal
>>>>>>> descriptor.
>>>>>>
>>>>>> The problem is not in the Loongson1B gmac.
>>>>>
>>>>> I found that the bit checksum_insertion is not existed in normal
>>>>> descriptor.
>>>>>
>>>>>> The normal descriptor fields in the stmmac refer to an old synopsys
>>>>>> databook.
>>>>>
>>>>> Could you send me the new databook of Synopsys GMAC?
>>>>>
>>>>>> New chips have the same structure you have added; so we should fix
>>>>>> this
>>>>>> in the driver w/o breaking the compatibility for old chips.
>>>>>
>>>>> Agree.
>>>>>
>>>>>> I kindly ask you to confirm if the currently normal descriptor
>>>>>> structure
>>>>>> (w/o your changes) doesn't work on your platform.
>>>>>> Did you test it?
>>>>>
>>>>> Well, the normal descriptor works on my platform except TX checksum
>>>>> offload.
>>>>
>>>> ok! I suspected that.
>>>>
>>>>
>>>>>>> Moreover, I want to enable the TX checksum offload function which is
>>>>>>> not supported in normal descriptor.
>>>>>>> Any suggestions?
>>>>>>
>>>>>> It is supported but you have to pass from the platform: tx_coe = 1.
>>>>>
>>>>> I noticed that the flag csum_insertion is passed to
>>>>> ndesc_prepare_tx_desc() in stmmac_xmit(). But ndesc_prepare_tx_desc()
>>>>> just ignores it.
>>>>> In other words, the TX checksum offload function is disabled in normal
>>>>> descriptor currently.
>>>>>
>>>>> Should we fix this problem for normal descriptor?
>>>>
>>>> Yes, we should. If you agree, I'll update the normal descriptor
>>>> structure to yours. This is the normal descriptor used in newer GMAC.
>>>> Tx csum will be done for normal descriptors in case of these GMAC
>>>> devices and not for old MAC10/100. For the MAC10/100 some bits for
>>>> normal descriptors are reserved and won't be used at all.
>>>>
>>>> I'll also verify that the patch doesn't break the back-compatibility
>>>> with old MAC10/100. I have the HW where doing the tests.
>>>>
>>>> After that, I'll prepare the patch for net-next and for your kernel.
>>>
>>> Hello Kelvin
>>>
>>> attached the patch tested on my development kernel.
>>> It runs fine on old and new mac devices.
>>>
>>> Can you try it on your side? Hmm, it is likely it won't apply fine on
>>> your tree but you know the changes ;-).
>>>
>>> If ok, I'll rework it for net-next and send it to the mailing list.
>>>
>>> Thanks
>>> Peppe
>>>
>>>>
>>>>>
>>>>>> Peppe
>>>>>>>
>>>>>>>> Note:
>>>>>>>> IIRC, there is a bit difference in case of normal descriptors for
>>>>>>>> Synopsys databook newer than the 1.91 (I used for testing this
>>>>>>>> mode).
>>>>>>>> In any case, I remember that, on some platforms, the normal
>>>>>>>> descriptors
>>>>>>>> have been used w/o problems also on these new chip generations.
>>>>>>>>
>>>>>>>> Peppe
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>>>> the body of a message to majordomo@vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>>
>>>
>>>
>>
>>
>
>
--
Best Regards!
Kelvin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
2011-10-21 17:33 ` Wu Zhangjin
@ 2011-11-16 14:10 ` Ralf Baechle
1 sibling, 0 replies; 19+ messages in thread
From: Ralf Baechle @ 2011-11-16 14:10 UTC (permalink / raw)
To: keguang.zhang; +Cc: linux-mips, linux-kernel, wuzhangjin, r0bertz
On Fri, Oct 21, 2011 at 06:28:06PM +0800, keguang.zhang@gmail.com wrote:
> Date: Fri, 21 Oct 2011 18:28:06 +0800
> From: keguang.zhang@gmail.com
> To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
> Cc: ralf@linux-mips.org, wuzhangjin@gmail.com, r0bertz@gentoo.org, Kelvin
> Cheung <keguang.zhang@gmail.com>
> Subject: [PATCH V2 2/4] MIPS: Add board support for Loongson1B
>
> From: Kelvin Cheung <keguang.zhang@gmail.com>
>
> This patch adds basic platform support for Loongson1B
> including serial port, ethernet, and interrupt handler.
>
> Loongson1B UART is compatible with NS16550A.
> Loongson1B GMAC is built around Synopsys IP Core.
>
> Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
> ---
> arch/mips/include/asm/mach-loongson1/irq.h | 68 +++++++++
> arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++
> arch/mips/include/asm/mach-loongson1/platform.h | 21 +++
> arch/mips/include/asm/mach-loongson1/prom.h | 24 +++
> arch/mips/include/asm/mach-loongson1/regs-clk.h | 32 ++++
> arch/mips/include/asm/mach-loongson1/regs-intc.h | 25 ++++
> arch/mips/include/asm/mach-loongson1/regs-wdt.h | 21 +++
> arch/mips/include/asm/mach-loongson1/war.h | 25 ++++
> arch/mips/loongson1/common/clock.c | 165 ++++++++++++++++++++++
> arch/mips/loongson1/common/irq.c | 136 ++++++++++++++++++
> arch/mips/loongson1/common/platform.c | 94 ++++++++++++
> arch/mips/loongson1/common/prom.c | 88 ++++++++++++
> arch/mips/loongson1/common/reset.c | 46 ++++++
> arch/mips/loongson1/common/setup.c | 29 ++++
> arch/mips/loongson1/ls1b/board.c | 31 ++++
> drivers/net/stmmac/descs.h | 68 +++++++++
> drivers/net/stmmac/enh_desc.c | 16 ++
I take it you've split off the stmac parts from this patch? Can you please
send an updated version of this patch or the entire series, if that should
be necessary?
Thanks,
Ralf
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2011-11-16 14:10 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-10-21 10:28 [PATCH V2 1/4] MIPS: Add CPU support for Loongson1B keguang.zhang
2011-10-21 10:28 ` [PATCH V2 2/4] MIPS: Add board " keguang.zhang
2011-10-21 17:33 ` Wu Zhangjin
2011-10-24 7:19 ` Giuseppe CAVALLARO
2011-10-24 10:36 ` Kelvin Cheung
2011-10-24 12:18 ` Giuseppe CAVALLARO
2011-10-24 14:05 ` Kelvin Cheung
2011-10-24 15:35 ` Giuseppe CAVALLARO
2011-10-25 2:12 ` Kelvin Cheung
2011-10-25 7:09 ` Giuseppe CAVALLARO
2011-10-25 8:20 ` Giuseppe CAVALLARO
2011-10-25 9:21 ` Kelvin Cheung
2011-10-26 4:27 ` Kelvin Cheung
2011-10-26 7:20 ` Giuseppe CAVALLARO
2011-10-26 7:48 ` Kelvin Cheung
2011-10-25 9:18 ` Kelvin Cheung
2011-11-16 14:10 ` Ralf Baechle
2011-10-21 10:28 ` [PATCH V2 3/4] MIPS: Add Makefile and Kconfig " keguang.zhang
2011-10-21 10:28 ` [PATCH V2 4/4] MIPS: Add defconfig " keguang.zhang
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