Re: [RFC PATCH] pciehp: Wait for link get trained in pci_check_link_status()

[Yinghai Lu <yinghai.lu@oracle.com>]

On 11/08/2011 01:19 AM, Kenji Kaneshige wrote:

> (2011/11/08 10:13), Yinghai Lu wrote:
>>
>> Found one PCI Express Modules has link training error after hotplug.
>> It turns out that after DLLLA is set, LT is still set for a while.
>> So pciehp will delcare that hotplug fail in 1s.
> 
> I think DLLLA bit reads 1b means LT is completed. So I don't know why LT
> is still set on your platform.


recovery training ?

> 
>>
>> HW guys say that pciehp is against PCI-e SPEC:
>>   From PCI Express Base Specification Revision 2.1, Section 6.7.3.3:
>>   Software must allow 1 second after the Data Link Layer Link Active bit reads 1b
>>   before it is permitted to determine that a hot plugged device which fails to
>>   return a Successful Completion for a Valid Configuration Request is a broken
>>   device (see section 6.6).
>>
>> Try to wait for long enough by adding LT checking in 1s.
> 
> The pciehp driver already have this 1 second wait in board_added().
> So I still don't understand what in pciehp is against PCIe spec clearly.
> Can you explain more about this?


should be fail in 1s after DLLLA, is set.

even we should not check LT, and should try pci conf reading to new added device.

> 
> What about the patch below? I think it's much simpler and has less impact.


Should work. will try it today.

Thanks

Yinghai Lu