From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Al Cooper <alcooperx@gmail.com>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: Kernel hangs occasionally during boot.
Date: Wed, 09 Nov 2011 15:26:32 +0400 [thread overview]
Message-ID: <4EBA6368.6030503@niisi.msk.ru> (raw)
In-Reply-To: <20111109103432.GA27378@linux-mips.org>
On 09.11.2011 14:34, Ralf Baechle wrote:
> Hmm... Looking at the R4000 manual which generall has the longest
> pipeline hazards, mtc0 gets executed at stage 7, interrupts get sampled
> at stage 3 meaning there is a (7 - 3 - 1) = 3 cycles hazard. Does
> that one statisfy your constraints? Or are additional cycles needed
> for a hazard that's generated outside of the CPU's pipeline?
In fact, current back_to_back_hazard is more than enough for cpus I deal
with. I guess, required time to wait equals number of stages between EX
(or RD) and WB stages for modern cpus, because CP0 CAUSE is updated
during WB nowadays.
I suspect, the time required to update internal counter logic for
original r4k might be bigger though. At least old code waited 12 cycles
(4*irq_disable_hazard which is 3 for r4k). Perhaps, we should keep this
code and insert the same amount of nops for old cpus at least.
Regards,
Gleb.
prev parent reply other threads:[~2011-11-09 11:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-08 14:59 [PATCH] MIPS: Kernel hangs occasionally during boot Al Cooper
2011-11-08 17:55 ` Ralf Baechle
2011-11-09 7:40 ` Gleb O. Raiko
2011-11-09 9:13 ` Ralf Baechle
2011-11-09 10:34 ` Ralf Baechle
2011-11-09 11:26 ` Gleb O. Raiko [this message]
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