[PATCH 1/2] gpio: enable SUS_GPIO[3:0] resume powered gpio, explicitly on Intel SCH.

[PATCH 1/2] gpio: enable SUS_GPIO[3:0] resume powered gpio, explicitly on Intel SCH.

[Denis Turischev]

Resume powered gpio pins SUS_GPIO[3:0] on Intel SCH may be
disabled by BIOS setting, need to enable them explicitly.

Signed-off-by: Denis Turischev <denis@compulab.co.il>
---
 drivers/gpio/gpio-sch.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index 8cadf4d..f287016 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -218,10 +218,9 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
 			 */
 			outb(0x3, gpio_ba + CGEN + 1);
 			/*
-			 * SUS_GPIO[2:0] enabled by default
-			 * Enable SUS_GPIO3 resume powered gpio explicitly
+			 * Enable SUS_GPIO[3:0] resume powered gpio explicitly
 			 */
-			outb(0x8, gpio_ba + RGEN);
+			outb(0xF, gpio_ba + RGEN);
 			break;
 
 		case PCI_DEVICE_ID_INTEL_ITC_LPC:
-- 
1.7.5.4

[PATCH 2/2] gpio: optimise gpio functionality in gpio-sch.c

[Denis Turischev]

GPIO logic of core powered and resume powered gpios on Intel SCH/Tunnel Creek
is the same, make wrappers for them with appropriate base registers.

Signed-off-by: Denis Turischev <denis@compulab.co.il>
---
 drivers/gpio/gpio-sch.c |   84 +++++++++++++++++++++-------------------------
 1 files changed, 38 insertions(+), 46 deletions(-)

diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index f287016..8377d28 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -41,14 +41,14 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 static unsigned short gpio_ba;
 
-static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned  gpio_num)
+static void sch_gpio_direction_in(unsigned ioreg, unsigned  gpio_num)
 {
 	u8 curr_dirs;
 	unsigned short offset, bit;
 
 	spin_lock(&gpio_lock);
 
-	offset = CGIO + gpio_num / 8;
+	offset = ioreg + gpio_num / 8;
 	bit = gpio_num % 8;
 
 	curr_dirs = inb(gpio_ba + offset);
@@ -57,29 +57,28 @@ static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned  gpio_num)
 		outb(curr_dirs | (1 << bit), gpio_ba + offset);
 
 	spin_unlock(&gpio_lock);
-	return 0;
 }
 
-static int sch_gpio_core_get(struct gpio_chip *gc, unsigned gpio_num)
+static int sch_gpio_get(unsigned lvreg, unsigned gpio_num)
 {
 	int res;
 	unsigned short offset, bit;
 
-	offset = CGLV + gpio_num / 8;
+	offset = lvreg + gpio_num / 8;
 	bit = gpio_num % 8;
 
 	res = !!(inb(gpio_ba + offset) & (1 << bit));
 	return res;
 }
 
-static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val)
+static void sch_gpio_set(unsigned lvreg, unsigned gpio_num, int val)
 {
 	u8 curr_vals;
 	unsigned short offset, bit;
 
 	spin_lock(&gpio_lock);
 
-	offset = CGLV + gpio_num / 8;
+	offset = lvreg + gpio_num / 8;
 	bit = gpio_num % 8;
 
 	curr_vals = inb(gpio_ba + offset);
@@ -91,17 +90,14 @@ static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val)
 	spin_unlock(&gpio_lock);
 }
 
-static int sch_gpio_core_direction_out(struct gpio_chip *gc,
-					unsigned gpio_num, int val)
+static void sch_gpio_direction_out(unsigned ioreg, unsigned gpio_num)
 {
 	u8 curr_dirs;
 	unsigned short offset, bit;
 
-	sch_gpio_core_set(gc, gpio_num, val);
-
 	spin_lock(&gpio_lock);
 
-	offset = CGIO + gpio_num / 8;
+	offset = ioreg + gpio_num / 8;
 	bit = gpio_num % 8;
 
 	curr_dirs = inb(gpio_ba + offset);
@@ -109,6 +105,30 @@ static int sch_gpio_core_direction_out(struct gpio_chip *gc,
 		outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
 
 	spin_unlock(&gpio_lock);
+}
+
+static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned  gpio_num)
+{
+	sch_gpio_direction_in(CGIO, gpio_num);
+	return 0;
+}
+
+static int sch_gpio_core_get(struct gpio_chip *gc, unsigned gpio_num)
+{
+	return sch_gpio_get(CGLV, gpio_num);
+}
+
+static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val)
+{
+	sch_gpio_set(CGLV, gpio_num, val);
+}
+
+static int sch_gpio_core_direction_out(struct gpio_chip *gc,
+					unsigned gpio_num, int val)
+{
+	sch_gpio_direction_out(CGIO, gpio_num);
+	sch_gpio_set(CGLV, gpio_num, val);
+
 	return 0;
 }
 
@@ -122,57 +142,29 @@ static struct gpio_chip sch_gpio_core = {
 };
 
 static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
-					unsigned gpio_num)
+					unsigned  gpio_num)
 {
-	u8 curr_dirs;
-
-	spin_lock(&gpio_lock);
-
-	curr_dirs = inb(gpio_ba + RGIO);
-
-	if (!(curr_dirs & (1 << gpio_num)))
-		outb(curr_dirs | (1 << gpio_num) , gpio_ba + RGIO);
-
-	spin_unlock(&gpio_lock);
+	sch_gpio_direction_in(RGIO, gpio_num);
 	return 0;
 }
 
 static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num)
 {
-	return !!(inb(gpio_ba + RGLV) & (1 << gpio_num));
+	return sch_gpio_get(RGLV, gpio_num);
 }
 
 static void sch_gpio_resume_set(struct gpio_chip *gc,
 				unsigned gpio_num, int val)
 {
-	u8 curr_vals;
-
-	spin_lock(&gpio_lock);
-
-	curr_vals = inb(gpio_ba + RGLV);
-
-	if (val)
-		outb(curr_vals | (1 << gpio_num), gpio_ba + RGLV);
-	else
-		outb((curr_vals & ~(1 << gpio_num)), gpio_ba + RGLV);
-
-	spin_unlock(&gpio_lock);
+	sch_gpio_set(RGLV, gpio_num, val);
 }
 
 static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
 					unsigned gpio_num, int val)
 {
-	u8 curr_dirs;
-
-	sch_gpio_resume_set(gc, gpio_num, val);
-
-	spin_lock(&gpio_lock);
-
-	curr_dirs = inb(gpio_ba + RGIO);
-	if (curr_dirs & (1 << gpio_num))
-		outb(curr_dirs & ~(1 << gpio_num), gpio_ba + RGIO);
+	sch_gpio_direction_out(RGIO, gpio_num);
+	sch_gpio_set(RGLV, gpio_num, val);
 
-	spin_unlock(&gpio_lock);
 	return 0;
 }
 
-- 
1.7.5.4