From: Alex Shi <alex.shi@intel.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: tglx@linutronix.de, hpa@zytor.com, mingo@redhat.com,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
x86@kernel.org, asit.k.mallick@intel.com
Subject: Re: change last level cache alignment on x86?
Date: Sat, 03 Mar 2012 19:30:03 +0800 [thread overview]
Message-ID: <4F5200BB.5090505@intel.com> (raw)
In-Reply-To: <20120302152506.GA14487@elte.hu>
On 03/02/2012 11:25 PM, Ingo Molnar wrote:
> * Alex Shi <alex.shi@intel.com> wrote:
>
>> So, with defconfig on x86_64, I saw much changes in System.map:
>> before patched after patched
>> ...
>> 000000000000b000 d tlb_vector_| 000000000000b000 d tlb_vector
>> 000000000000b080 d cpu_loops_p| 000000000000b040 d cpu_loops_
>> ...
> Ok, mind sending a patch, changelogged, with a SOB?
Thanks a lot for review! A patch was sent to you.
> Thanks,
>
> Ingo
prev parent reply other threads:[~2012-03-03 11:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-01 8:33 change last level cache alignment on x86? Alex,Shi
2012-03-02 7:30 ` Alex Shi
2012-03-02 8:12 ` Ingo Molnar
2012-03-02 14:42 ` Alex Shi
2012-03-02 15:25 ` Ingo Molnar
2012-03-03 11:30 ` Alex Shi [this message]
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