From: Aneesh V <aneesh@ti.com>
To: Greg KH <greg@kroah.com>
Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org
Subject: Re: [PATCH 0/8] Add TI EMIF SDRAM controller driver
Date: Fri, 09 Mar 2012 09:29:36 +0530 [thread overview]
Message-ID: <4F598028.5020509@ti.com> (raw)
In-Reply-To: <20120308205944.GB16644@kroah.com>
On Friday 09 March 2012 02:29 AM, Greg KH wrote:
> On Thu, Mar 08, 2012 at 09:24:17PM +0530, Aneesh V wrote:
>> Add a driver for the EMIF SDRAM controller used in TI SoCs
>>
>> EMIF is an SDRAM controller that supports, based on its revision,
>> one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
>> for LPDDR2.
>>
>> The driver supports the following features:
>> - Calculates the DDR AC timing parameters to be set in EMIF
>> registers using data from the device data-sheets and based
>> on the DDR frequency. If data from data-sheets is not available
>> default timing values from the JEDEC spec are used. These
>> will be safe, but not necessarily optimal
>> - API for changing timings during DVFS or at boot-up
>> - Temperature alert configuration and handling of temperature
>> alerts, if any for LPDDR2 devices
>> * temperature alert is based on periodic polling of MR4 mode
>> register in DDR devices automatically performed by hardware
>> * timings are de-rated and brought back to nominal when
>> temperature raises and falls respectively
>> - Cache of calculated register values to avoid re-calculating
>> them
>>
>> The driver will need some minor updates when it is eventually
>> integrated with Dynamic Voltage and Frequency Scaling (DVFS).
>> This can not be done now as DVFS support is not available in
>> the mainline yet.
>
> What will need to be updated in it? The userspace interface or
> something else?
The driver will need to register notifiers with regulator framework and
clock framework respectively for voltage and frequency notifications.
Also a hook will be needed for initiating the hardware sequence for
updating the AC timings. This process is under the control of Power
Reset and Clock Management(PRCM) module of OMAP.
>
> Why not wait until that code is accepted, it should be going into 3.4,
> right?
As Paul mentioned Core DVFS may take longer time. Besides, EMIF driver
is a pre-requisite for correct functioning of Core DVFS.
thanks,
Aneesh
next prev parent reply other threads:[~2012-03-09 3:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-08 15:54 [PATCH 0/8] Add TI EMIF SDRAM controller driver Aneesh V
2012-03-08 15:54 ` [PATCH 1/8] OMAP4: hwmod: add EMIF hw mod data Aneesh V
2012-03-08 16:41 ` Cousson, Benoit
2012-03-08 16:43 ` Aneesh V
2012-03-08 15:54 ` [PATCH 2/8] misc: ddr: add LPDDR2 data from JESD209-2 Aneesh V
2012-03-08 15:54 ` [PATCH 3/8] misc: emif: add register definitions for EMIF Aneesh V
2012-03-08 15:54 ` [PATCH 4/8] misc: emif: add basic infrastructure for EMIF driver Aneesh V
2012-03-08 15:54 ` [PATCH 5/8] misc: emif: handle frequency and voltage change events Aneesh V
2012-03-08 15:54 ` [PATCH 6/8] misc: emif: add interrupt and temperature handling Aneesh V
2012-03-08 15:54 ` [PATCH 7/8] misc: emif: add one-time settings Aneesh V
2012-03-08 15:54 ` [PATCH 8/8] misc: emif: add debugfs entries for emif Aneesh V
2012-03-08 20:59 ` [PATCH 0/8] Add TI EMIF SDRAM controller driver Greg KH
2012-03-08 21:47 ` Paul Walmsley
2012-03-09 3:59 ` Aneesh V [this message]
2012-03-12 15:58 ` Santosh Shilimkar
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