From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754093Ab2DBSLC (ORCPT ); Mon, 2 Apr 2012 14:11:02 -0400 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183]:20491 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754026Ab2DBSK6 (ORCPT ); Mon, 2 Apr 2012 14:10:58 -0400 X-SpamScore: -10 X-BigFish: VPS-10(zzbb2dI1432N98dKzz1202hzzz2dh668h839hd25h) X-Forefront-Antispam-Report: CIP:163.181.249.109;KIP:(null);UIP:(null);IPV:NLI;H:ausb3twp02.amd.com;RD:none;EFVD:NLI X-WSS-ID: 0M1V6I0-02-2FQ-02 X-M-MSG: Message-ID: <4F79EBAA.7040602@amd.com> Date: Mon, 2 Apr 2012 14:10:50 -0400 From: Boris Ostrovsky User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111101 SUSE/3.1.16 Thunderbird/3.1.16 MIME-Version: 1.0 To: Tony Luck CC: Len Brown , , , , Len Brown Subject: Re: [PATCH 58/76] idle, x86: Allow off-lined CPU to enter deeper C states References: <09f98a825a821f7a3f1b162f9ed023f37213a63b.1333101989.git.len.brown@intel.com> <1333102459-23750-1-git-send-email-lenb@kernel.org> <1a022e3f1be11730bd8747b1af96a0274bf6356e.1333101989.git.len.brown@intel.com> <4F79E83C.5090506@amd.com> In-Reply-To: Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/02/12 14:02, Tony Luck wrote: >> x86 halt() causes processor to go to C1 state (which is often not the >> deepest). But other than that it seems similar to what you are describing. > > OK - then Konrad's suggestion of using "safe_halt()" here rather than > "halt()" would work for ia64. I originally didn't want to use safe_halt() because the CPU will wake up on an unmasked HW interrupt unlike halt(). But I guess we are not supposed to get any such interrupts when we are off-lining a CPU so safe_halt() should be OK. Thanks. -boris