Re: [PATCH 2/2] x86/mce: Add instruction recovery signatures to mce-severity table

[Chen Gong <gong.chen@linux.intel.com>]

于 2012/5/11 2:12, Tony Luck 写道:
> Instruction recovery cases are very similar to the data recovery one
> we already have. Just trade out for a new MCACOD value.
> 
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce-severity.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> index 0c82091..163c4364ca 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> @@ -126,6 +126,16 @@ static struct severity {
>  		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
>  		USER
>  		),
> +	MCESEV(
> +		KEEP, "HT thread notices Action required: instruction fetch error",
> +		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
> +		MCGMASK(MCG_STATUS_EIPV, 0)
> +		),
> +	MCESEV(
> +		AR, "Action required: instruction fetch error",
> +		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
> +		USER
> +		),
>  #endif
>  	MCESEV(
>  		PANIC, "Action required: unknown MCACOD",

For IFU, on affected logical processors, RIPV and EIPV both are 0,
since now new IFU entries are added into severity table, the old
entry as below should be removed:

/* Neither return not error IP -- no chance to recover -> PANIC */
        MCESEV(
                PANIC, "Neither restart nor error IP",
                MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
                ),