Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblings of SMT

[Arjan van de Ven <arjan@linux.intel.com>]

On 5/24/2012 6:23 AM, Peter Zijlstra wrote:
> On Thu, 2012-05-24 at 06:19 -0700, Andrew Lutomirski wrote:
>>
>> A decent heuristic might be to prefer idle SMT siblings for TLB
>> invalidation.  I don't know what effect that would have on power
>> consumption (it would be rather bad if idling one SMT thread while the
>> other one is busy saves much power). 

we really really shouldn't do flushing of tlb's on only one half of SMT.
SMT sibblings have their own TLB pool at least on some of Intels chips.

Also, note that on anything sane, we flush the tlb's in software before
going to an Idle state, so that we don't have to wake idle cpus up to
flush their TLBs (except for "global tlbs", but those change very very
very rarely hopefully)

> 
> Right, I've never really understood how C-states and SMT go together.
> Arjan recently implied waking a thread sibling from C-state was
> 'expensive' which on first thought seems daft, the core is running
> already.

in order to wake *anything* you need to send an IPI to it, it has to
exit the idle loop etc etc. It's not expensive-expensive, but it
certainly is not free either.