Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblings of SMT

[Alex Shi <alex.shi@intel.com>]

>>> we really really shouldn't do flushing of tlb's on only one half of SMT.

>>> SMT sibblings have their own TLB pool at least on some of Intels chips.
>>
>>
>> That is also the biggest question I want to know. Actually, some
>> documents, wiki said the SMT sibling just has process registers and
>> interrupt part, no any tlb/l1 cache etc, (like intel's doc
>> vol6iss1_hyper_threading_technology.pdf).  And the patch runs well on
>> NHM EP/WSM EP/NHM EX/SNB EP CPUs.
>>
>> But hard to get such clearly per cpu info of SMT/HT, so, what the
>> detailed Intel chips has 'TLB pool' on SMT?
> 
> all of them.
> 
> the TLB pool is shared as physical resource (dynamic or static, that
> depends), but each tlb entry will be tagged for which of the two HT
> pairs it's for, and on a logical level, they are completely separate as
> a result (as they should be)


But, why just flush part of SMT doesn't crash kernel on many benchmarks
testing? Does it means flush tlb without PCID (doesn't enable in current
kernel) will flush both of 'TLB pool'?

Oh, lots of questions of the TLB pool details. :) Could you like share
the URL of related documents?


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