Re: perf, x86: only do lbr init if bts is available

[David Ahern <dsahern@gmail.com>]

On 5/24/12 10:35 AM, Stephane Eranian wrote:
> Well, no. There is no connection between BTS and LBR and you're creating one.

Ok. That was not clear to me from skimming the manual.
Then should it be tied to X86_FEATURE_DTES64?

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c 
b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..1090ae6 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -640,6 +640,9 @@ void intel_pmu_lbr_init_core(void)
  /* nehalem/westmere */
  void intel_pmu_lbr_init_nhm(void)
  {
+   if (!boot_cpu_has(X86_FEATURE_DTES64))
+       return;
+
     x86_pmu.lbr_nr     = 16;
     x86_pmu.lbr_tos    = MSR_LBR_TOS;
     x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;


> Where is the wrmsr coming from? What we need to do is ensure that LBR is not
> touched if we don't actually use it.

e.g., intel_pmu_lbr_init_nhm sets up lbr_nr, lbr_from, lbr_to and from, 
etc. Fhat I can tell intel_pmu_lbr_reset() gets invoked some where 
during the VM boot; I haven't traced how/when yet.

David