From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964863Ab2EXRHg (ORCPT ); Thu, 24 May 2012 13:07:36 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:44482 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933807Ab2EXRHf (ORCPT ); Thu, 24 May 2012 13:07:35 -0400 Message-ID: <4FBE6AD2.6050501@gmail.com> Date: Thu, 24 May 2012 11:07:30 -0600 From: David Ahern User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.7; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: Stephane Eranian CC: Peter Zijlstra , LKML , Gleb Natapov , Avi Kivity Subject: Re: perf, x86: only do lbr init if bts is available References: <4FBE5FA6.5050802@gmail.com> <4FBE64D0.7040507@gmail.com> In-Reply-To: <4FBE64D0.7040507@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/24/12 10:41 AM, David Ahern wrote: > On 5/24/12 10:35 AM, Stephane Eranian wrote: >> Where is the wrmsr coming from? What we need to do is ensure that LBR >> is not >> touched if we don't actually use it. > > e.g., intel_pmu_lbr_init_nhm sets up lbr_nr, lbr_from, lbr_to and from, > etc. Fhat I can tell intel_pmu_lbr_reset() gets invoked some where > during the VM boot; I haven't traced how/when yet. [ 0.012998] [] intel_pmu_lbr_reset+0x2a/0xa0 [ 0.012998] [] intel_pmu_cpu_starting+0x3b/0x100 [ 0.012998] [] ? allocate_shared_regs+0x20/0x50 [ 0.012998] [] x86_pmu_notifier+0xb3/0xc0 [ 0.012998] [] init_hw_perf_events+0x42c/0x456 [ 0.012998] [] do_one_initcall+0x34/0x170 [ 0.012998] [] ? native_smp_prepare_cpus+0x2b7/0x2f2 [ 0.012998] [] ? check_bugs+0xf9/0xf9 [ 0.012998] [] kernel_init+0x77/0x1a4 [ 0.012998] [] ? start_kernel+0x36d/0x36d [ 0.012998] [] kernel_thread_helper+0x6/0x10