From: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
To: Ira Weiny <ira.weiny@intel.com>,
linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: Re: [PATCH 4/4] acpi/ghes, cxl/pci: Trace FW-First CXL Protocol Errors
Date: Wed, 3 Jan 2024 13:13:53 -0800 [thread overview]
Message-ID: <4a69aa48-bf42-2815-863c-0caefdb23c68@amd.com> (raw)
In-Reply-To: <659471b5f33bc_151dc129479@iweiny-mobl.notmuch>
On 1/2/2024 12:27 PM, Ira Weiny wrote:
> Smita Koralahalli wrote:
>> When PCIe AER is in FW-First, OS should process CXL Protocol errors from
>> CPER records. These CPER records obtained from GHES module, will rely on
>> a registered callback to be notified to the CXL subsystem in order to be
>> processed.
>>
>> Call the existing cxl_cper_callback to notify the CXL subsystem on a
>> Protocol error.
>>
>> The defined trace events cxl_aer_uncorrectable_error and
>> cxl_aer_correctable_error currently trace native CXL AER errors. Reuse
>> them to trace FW-First Protocol Errors.
>>
>> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
>
> [snip]
>
>> int cxl_cper_register_callback(cxl_cper_callback callback)
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 37e1652afbc7..da516982a625 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -6,6 +6,7 @@
>> #include <linux/pci.h>
>> #include <linux/pci-doe.h>
>> #include <linux/aer.h>
>> +#include <linux/cper.h>
>> #include <cxlpci.h>
>> #include <cxlmem.h>
>> #include <cxl.h>
>> @@ -836,6 +837,51 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);
>>
>> +#define CXL_AER_UNCORRECTABLE 0
>> +#define CXL_AER_CORRECTABLE 1
>
> Better defined as an enum?
Will change.
>
>> +
>> +int cper_severity_cxl_aer(int cper_severity)
>
> My gut says that it would be better to hide this conversion in the
> GHES/CPER code and send a more generic defined CXL_AER_* severity through.
Ok will change.
>
>> +{
>> + switch (cper_severity) {
>> + case CPER_SEV_RECOVERABLE:
>> + case CPER_SEV_FATAL:
>> + return CXL_AER_UNCORRECTABLE;
>> + default:
>> + return CXL_AER_CORRECTABLE;
>> + }
>> +}
>> +
>> +void cxl_prot_err_trace_record(struct cxl_dev_state *cxlds,
>> + struct cxl_cper_rec_data *data)
>> +{
>> + struct cper_cxl_event_sn *dev_serial_num = &data->rec.hdr.dev_serial_num;
>> + u32 status, fe;
>> + int severity;
>> +
>> + severity = cper_severity_cxl_aer(data->severity);
>> +
>> + cxlds->serial = (((u64)dev_serial_num->upper_dw << 32) |
>> + dev_serial_num->lower_dw);
>
> This permanently overwrites the serial number read from PCI...
>
> If the serial number does not match up or was not valid (per the check in
> the previous patch) lets add a warning.
Sure will add.
Thanks,
Smita
>
> AFAICT they should match.
>
> Ira
>
> [snip]
>
prev parent reply other threads:[~2024-01-03 21:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 15:09 [PATCH 0/4] acpi/ghes, cper, cxl: Trace FW-First CXL Protocol Errors Smita Koralahalli
2024-01-02 15:09 ` [PATCH 1/4] acpi/ghes, cxl: Create a common CXL struct to handle different CXL CPER records Smita Koralahalli
2024-01-02 16:23 ` Ira Weiny
2024-01-03 20:04 ` Smita Koralahalli
2024-01-03 20:35 ` Ira Weiny
2024-01-02 15:09 ` [PATCH 2/4] efi/cper, cxl: Make definitions and structures global Smita Koralahalli
2024-01-02 16:30 ` Ira Weiny
2024-01-03 20:16 ` Smita Koralahalli
2024-01-03 22:30 ` Ira Weiny
2024-01-02 15:09 ` [PATCH 3/4] acpi/ghes, efi/cper: Recognize and process CXL Protocol Errors Smita Koralahalli
2024-01-02 17:58 ` Ira Weiny
2024-01-03 21:12 ` Smita Koralahalli
2024-01-03 22:32 ` Ira Weiny
2024-01-02 15:09 ` [PATCH 4/4] acpi/ghes, cxl/pci: Trace FW-First " Smita Koralahalli
2024-01-02 20:27 ` Ira Weiny
2024-01-03 21:13 ` Smita Koralahalli [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4a69aa48-bf42-2815-863c-0caefdb23c68@amd.com \
--to=smita.koralahallichannabasappa@amd.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=alison.schofield@intel.com \
--cc=ardb@kernel.org \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-efi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
--cc=yazen.ghannam@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox