Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Hans Zhang <hans.zhang@cixtech.com>]

On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>> Document the compatible property for the newly added values for PCIe EP and
>> RP configurations. Fix the compilation issues that came up for the existing
>> Cadence bindings
>>
>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>> ---
>>   .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>   .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>   2 files changed, 110 insertions(+), 21 deletions(-)
> 
> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
> known), so you really need to fix your mailing setup or use b4 relay.
> 

Hi Krzysztof,

I have obtained Manikandan's consent and we will collaborate to submit 
the series patch. Our Cixtech P1 (internal name sky1) is currently 
upstream. Because I need upstream Cadence root port driver, However, the 
Cadence common code of the current linux master does not support 
HPA[High Performance Architecture IP] is the second generation of 
cadence PCIe IP. Subsequently, I will send git send-email to pci mail list.

Peter Chen patchs:
https://patchwork.kernel.org/project/linux-arm-kernel/cover/20250324062420.360289-1-peter.chen@cixtech.com/

Best regards,
Hans