Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller

["Shenhar, Talel" <talel@amazon.com>]

On 1/2/2023 2:47 PM, Krzysztof Kozlowski wrote:
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> On 02/01/2023 13:17, Shenhar, Talel wrote:
>> Hi,
>>
>> Want to consult on a topic that involve both drivers/memory and
>> drivers/edac.
>>
>> * We want to introduce driver that reads DDR controller RAS register and
>> notify for ECC errors by using EDAC MC API found in drivers/edac.
>> * We also want to have a capability to dynamically change DDR refresh
>> rate based on thermal values (best to be done in drivers/memory ?).
>>
>> The pain point here is that both capabilities are controlled from the
>> DDR controller.
>> This create issue while using
>> devm_platform_ioremap_resource*->devm_request_mem_region which prevent
>> two mapping of same area.
> This could be avoided but the true problem is that you have two devices
> for same memory mapping. Devicetree does not allow it and it points to
> some wrong hardware representation in DTS.
>
>> It seems to be expected problem as we have 2 "framework" (edac and
>> memory) split while both aim for same HW unit.
>> What is the recommended way to face such conflicts?
> You now mix Devicetree and Linux drivers. You can have same IO address
> space used by multiple drivers, even though it is not always good
> approach (concurrent and conflicting change of same settings).
>
> HW description is irrelevant to this.
>
>> We had several concept in mind but would love to get your point of view
>> first.
> Describe hardware accurately and completely. This solves all the
> problems, doesn't it? Linux drivers do not depend on it and you can make
> it differently.

Describing the hardware accurately and completely means to have multiple 
reg property in the device-tree, right?

That way we will split the HW description to smaller bits rather then 
just big "ddrc", and that shall allow us to have two drivers and each 
one will get its own share of the split, right?

That was the intent of solution 1 below.

>
>> Things we had in mind:
>> 1) map more specific region to avoid conflict (we don't need the same
>> registers on both entity so if we do very specific multiple mapping this
>> shall be resolved)
>> 2) use other kernel API for mapping that doesn't do request_mem_region
>> (or use the reserve only for one of them)
>> 3) have single driver (edac mc) handle also the refresh rate
>> 4) export edac_mc.h and have the drivers/memory have all the needed code
>> to do both edac and refresh rate under drivers/memory
> None of these address the core problem - possibly inaccurate hardware
> description...

Can you elaborate on this inaccurate hardware description?

Also, I'd like to write down my understanding of your response from above:

it seems you see as possible solution both using different API that 
allow overlapping (solution 2) and also for splitting the IO address 
space to finer pieces to achieve full HW description (solution 1)

>
> Best regards,
> Krzysztof
>