From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754633AbdLFJbu (ORCPT ); Wed, 6 Dec 2017 04:31:50 -0500 Received: from smtp-out4.electric.net ([192.162.216.183]:53216 "EHLO smtp-out4.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753998AbdLFJbr (ORCPT ); Wed, 6 Dec 2017 04:31:47 -0500 From: David Laight To: "'Alan Tull'" , Wu Hao CC: "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-api@vger.kernel.org" , "luwei.kang@intel.com" , "yi.z.zhang@intel.com" , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , "Xiao Guangrong" Subject: RE: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Thread-Topic: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Thread-Index: AQHTZ0zlT9aHswbrXkGWaDG3vrBCQaMoBU+ggAudum2AAnYfkA== Date: Wed, 6 Dec 2017 09:31:57 +0000 Message-ID: <4c45380a630b4927b4de97114b508f1a@AcuMS.aculab.com> References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> <1511764948-20972-9-git-send-email-hao.wu@intel.com> <20171128031519.GA25705@hao-dev> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.33] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-Outbound-IP: 156.67.243.126 X-Env-From: David.Laight@ACULAB.COM X-Proto: esmtps X-Revdns: X-HELO: AcuMS.aculab.com X-TLS: TLSv1.2:ECDHE-RSA-AES256-SHA384:256 X-Authenticated_ID: X-PolicySMART: 3396946, 3397078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id vB69VxZZ000627 From: Alan Tull > Sent: 04 December 2017 19:47 > > On Mon, Nov 27, 2017 at 9:15 PM, Wu Hao wrote: > > On Mon, Nov 27, 2017 at 10:28:04AM +0000, David Laight wrote: > >> From: Wu Hao > >> > Sent: 27 November 2017 06:42 > >> > From: Zhang Yi > >> > > >> > The Intel FPGA device appears as a PCIe device on the system. This patch > >> > implements the basic framework of the driver for Intel PCIe device which > >> > is located between CPU and Accelerated Function Units (AFUs), and has > >> > the Device Feature List (DFL) implemented in its MMIO space. > >> > >> This ought to have a better name than 'Intel FPGA'. > >> An fpga can be used for all sorts of things, this looks like > >> a very specific architecture using a common VHDL environment to > >> allow certain types of user VHDL be accessed over PCIe. > > > > Hi David > > > > This patch adds a pcie device driver for Intel FPGA devices which implements > > the DFL, e.g Intel Server Platform with In-package FPGA and Intel FPGA PCIe > > Acceleration Cards. They are pcie devices, and all have DFL implemented in > > the MMIO space, so we would like to use one kernel driver to handle them. > > > > With this full patchset, it just provides user the interfaces to configure > > and access the FPGA accelerators on Intel DFL based FPGA devices. For sure, > > users can develop and build their own logics via tools provided by Intel, > > program them to accelerators on these Intel FPGA devices, and access them > > for their workloads. > > I don't see anything Intel specific here. This could all be named dfl-* Indeed, doesn't even seem to have to be implemented in an fpga. It might also not be the only device that implements DFL. You really need a name for your DFL acceleration implementation/interface. We make a board that uses an Intel/Altera fpga as a PCIe device, won't look anything like your one! David