From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2A7B341046 for ; Thu, 29 Jan 2026 16:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769704665; cv=none; b=Q51WpUyGRm+C6VsK5VtiETWZFHrfIOxBozwdQF8Bz9s3A0WgBw+69NBoFItN2gS8teS6xFKfUVg8+OcELBXF/fn0GeU/DNxsg3f7b7zn5q5KH3BXfLVtXJaz7tNsymeP2iZuS50clGRdI52qisTI3HT2bPktfHnB/nA20ran9rQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769704665; c=relaxed/simple; bh=AFilvSBaDZg5e3/ubwugKTf9lRDn9QJUzM20M1hM+DQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NbdEftowmchZtPMUEnuwhGoS3y+S6lpL1EaGTpk69Mr1MXbFUMy21j/EsPrlXsOrhHWQ7yyw8OF7PdHTiLKsdBzbHRIsV3h4JEIWxDg7zqx9bfy4bzTjWlYMZelz1E0s9XoUyKsyXs2DCr3i+Fx5alcWL45OJQt8l9fJVvVsfTA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iAMI9ffs; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iAMI9ffs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769704663; x=1801240663; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=AFilvSBaDZg5e3/ubwugKTf9lRDn9QJUzM20M1hM+DQ=; b=iAMI9ffsfKNbuGKzc+Nqi8Snqn5TQOmk+9c5CE2zWZ6EVnJXzeDI+ate XTE3g+N3g2tVCCP2cI7xHQzmtfq2m/T3kp5heYcvVfMCzh1M8qHKsV+nF ukxj7DdV7W3wzAabRmt2wnI4Fn8+CjUjMpFEyIuOrxEZ7sV1eiRfcFxAk HxqKMfC1/3c1Sh6Rf3DcIomP1UDVUXupBz6ZyyFJqiQG91hoJ4XD9Eq3p TXMnvDIDNjUQhbM+DDvbFmj+fLOs70c116l0k8vGnQbv+mWzt6+DkRMol dwwg+9aAIeJ16wftgdhKe5kt6NHrlk/KPtUqg1LrFOOZOSEXFB92KoWqN A==; X-CSE-ConnectionGUID: nchDXgFqTFmKXP7+AvV+SA== X-CSE-MsgGUID: 3ly1IsRgROaYkFhX8tPXkw== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="73543319" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="73543319" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 08:37:42 -0800 X-CSE-ConnectionGUID: Yn9f/pSgSpiO/9aUDg0vhQ== X-CSE-MsgGUID: x9D0kHRZSzOh3ZSeJIre4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="239348746" Received: from rchatre-mobl4.amr.corp.intel.com (HELO [10.125.109.237]) ([10.125.109.237]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 08:37:41 -0800 Message-ID: <4da8a846-d4c5-4ff9-a50b-4ea94dab14d7@intel.com> Date: Thu, 29 Jan 2026 08:37:41 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu/intel: Add RFDS mitigation quirk for Goldmont and Tremont-D To: moontorise@cfg.kr, x86@kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen Cc: "H . Peter Anvin" , Peter Zijlstra , Pawan Gupta , Josh Poimboeuf , linux-kernel@vger.kernel.org References: <20260129154342.3867-1-moontorise@cfg.kr> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzUVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT7CwXgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lczsFNBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABwsFfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y In-Reply-To: <20260129154342.3867-1-moontorise@cfg.kr> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/29/26 07:43, moontorise@cfg.kr wrote: > Intel's "Guidance for Security Issues on Intel Processors" [1] lists > Goldmont (06_5CH) and Tremont-D (06_86H) as capable of mitigating > Register File Data Sampling (RFDS) [2] starting from specific microcode > revisions as defined in the consolidated product CPU model table. I went looking and wasn't able to find this. It's also not clear which specific microcode version is/was connected to the RFDS mitigation. I rather dislike that table. I also don't see a microcode update for INTEL_ATOM_TREMONT_D ever having been published: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.git which makes me a bit suspicious. That would _seem_ to mean that everything on that CPU is BIOS-loaded or that no update has ever been published. If there's never been an update, then there's no reason for us to check the microcode version. > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 63b0f9aa9b3e..3480d9ddc046 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -513,6 +513,7 @@ > * and purposes if CLEAR_CPU_BUF_VM is set). > */ > #define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */ > +#define X86_FEATURE_RFDS_CLEAR (21*32+21) /* Clear register file via VERW */ > > /* > * BUG word(s) > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > index 83f51cab0b1e..20c1fa47f04b 100644 > --- a/arch/x86/kernel/cpu/bugs.c > +++ b/arch/x86/kernel/cpu/bugs.c > @@ -650,7 +650,8 @@ static const char * const rfds_strings[] = { > > static inline bool __init verw_clears_cpu_reg_file(void) > { > - return (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR); > + /* Check the synthetic flag for CPUs not reporting RFDS_CLEAR via MSR. */ > + return (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) || boot_cpu_has(X86_FEATURE_RFDS_CLEAR); > } Please don't do this. Just axe verw_clears_cpu_reg_file(). Move over to only checking X86_FEATURE_RFDS_CLEAR only. This patch should be broken into two. The first patch does this move, and adds: if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) setup_force_cpu_cap(X86_FEATURE_RFDS_CLEAR); > static void __init rfds_select_mitigation(void) > diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c > index 646ff33c4651..02f4ac2069f8 100644 > --- a/arch/x86/kernel/cpu/intel.c > +++ b/arch/x86/kernel/cpu/intel.c > @@ -325,6 +325,22 @@ static void early_init_intel(struct cpuinfo_x86 *c) > setup_clear_cpu_cap(X86_FEATURE_PGE); > } > > + /* > + * Goldmont and Tremont-D support RFDS mitigation via VERW, > + * but do not enumerate it in MSRs. Explicitly set the capability > + * based on the microcode revision. (Tremont-D requires stepping 7). > + */ > + switch (c->x86_vfm) { > + case INTEL_ATOM_GOLDMONT: > + if (c->microcode >= 0x28) > + set_cpu_cap(c, X86_FEATURE_RFDS_CLEAR); > + break; > + case INTEL_ATOM_TREMONT_D: > + if (c->x86_stepping == 7 && c->microcode >= 0x4c000026) > + set_cpu_cap(c, X86_FEATURE_RFDS_CLEAR); > + break; > + } No, this just isn't how we do these. Please make an x86_cpu_id[] array and use x86_match_cpu() on it. You can even match on steppings in those. I also despise these microcode version lists. Let's just use: boot_cpu_has_bug(X86_BUG_OLD_MICROCODE);