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X-CSE-ConnectionGUID: sgpDDlAcQASJ3i4aNPJH1g== X-CSE-MsgGUID: Wp0+yWkTSsOHnmlBG31rbg== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38512302" X-IronPort-AV: E=Sophos;i="6.13,242,1732608000"; d="scan'208";a="38512302" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 14:08:15 -0800 X-CSE-ConnectionGUID: 87E8zXR2RUaZNt58BW9Etw== X-CSE-MsgGUID: gU+yM5wPQFG5bCzfkBF6sA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,242,1732608000"; d="scan'208";a="113893048" Received: from eamartin-mobl1.amr.corp.intel.com (HELO [10.125.108.44]) ([10.125.108.44]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 14:08:12 -0800 Message-ID: <4e07bbe6-9f74-45e5-b8d4-f992d2be78fc@intel.com> Date: Tue, 28 Jan 2025 14:08:12 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] x86/tdx: Route safe halt execution via tdx_safe_halt To: Vishal Annapurve , x86@kernel.org, linux-kernel@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, erdemaktas@google.com, ackerleytng@google.com, jxgao@google.com, sagis@google.com, oupton@google.com, pgonda@google.com, kirill@shutemov.name, dave.hansen@linux.intel.com, linux-coco@lists.linux.dev, chao.p.peng@linux.intel.com, isaku.yamahata@gmail.com References: <20250128213652.1880545-1-vannapurve@google.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/28/25 13:36, Vishal Annapurve wrote: > Direct HLT instruction execution causes #VEs for TDX VMs which is routed > to hypervisor via tdvmcall. This process renders HLT instruction > execution inatomic, so any preceeding instructions like STI/MOV SS will > end up enabling interrupts before the HLT instruction is routed to the > hypervisor. This creates scenarios where interrupts could land during > HLT instruction emulation without aborting halt operation leading to > idefinite halt wait times. Could you please break out the spell checker before posting v2? There are a couple problems in that paragraph. > x86_idle is already upgraded to invoke tdx_safe_halt to avoid such Please add parenthesis to functions() to make it more clear what you are referring to. > scenarios, but it didn't cover pvnative_safe_halt which can be invoked > using raw_safe_halt from call sites like acpi_safe_halt (acpi_pm > subsystem). This patch upgrades the safe_halt executions to use > tdx_safe_halt. No "this patch", please. > To avoid future call sites which cause HLT instruction emulation with > irqs enabled, add a warn and fail the HLT instruction emulation. This seems like a bug fix. Shouldn't it have a cc:stable@ and a Fixes: tag? Do you have any thoughts on why nobody has hit this up to now? Are TDX users not enabling PARAVIRT_XXL? Not using ACPI? > diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c > index 0d9b090b4880..98b5f317596d 100644 > --- a/arch/x86/coco/tdx/tdx.c > +++ b/arch/x86/coco/tdx/tdx.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -380,6 +381,11 @@ static int handle_halt(struct ve_info *ve) > { > const bool irq_disabled = irqs_disabled(); > > + if (!irq_disabled) { > + WARN(1, "HLT instruction emulation unsafe with irqs enabled\n"); > + return -EIO; > + } Yeah, this warning is a good idea. But probably best left as a WARN_ONCE() so it doesn't spew too badly. > @@ -1083,6 +1089,15 @@ void __init tdx_early_init(void) > x86_platform.guest.enc_kexec_begin = tdx_kexec_begin; > x86_platform.guest.enc_kexec_finish = tdx_kexec_finish; > > +#ifdef CONFIG_PARAVIRT_XXL > + /* > + * halt instruction execution is not atomic for TDX VMs as it generates > + * #VEs, so otherwise "safe" halt invocations which cause interrupts to > + * get enabled right after halt instruction don't work for TDX VMs. > + */ > + pv_ops.irq.safe_halt = tdx_safe_halt; > +#endif The basic bug here was that there was a path to a hlt instruction that folks didn't realize. This patch fixes the basic bug and gives us a nice warning if there are additional paths that weren't imagined. But it doesn't really help us audit the code to make it clear that TDX guest kernel's _can't_ screw up hlt again the same way. This, for instance would make it pretty clear: static __always_inline void native_safe_halt(void) { if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) tdx_safe_halt(); mds_idle_clear_cpu_buffers(); asm volatile("sti; hlt": : :"memory"); } There are reasons we wouldn't want to do that exactly, but I'd much prefer something that is harder to screw up than the proposal above. Anybody have any better ideas?