From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com,
tony.luck@intel.com, babu.moger@amd.com, fenghuay@nvidia.com,
peternewman@google.com, zide.chen@intel.com,
dapeng1.mi@linux.intel.com, ben.horgan@arm.com,
yu.c.chen@intel.com, jason.zeng@intel.com,
linux-kselftest@vger.kernel.org,
LKML <linux-kernel@vger.kernel.org>,
patches@lists.linux.dev
Subject: Re: [PATCH v3 08/10] selftests/resctrl: Remove requirement on cache miss rate
Date: Fri, 27 Mar 2026 19:45:50 +0200 (EET) [thread overview]
Message-ID: <4e3b5362-e751-03a4-f98c-a760ad274d02@linux.intel.com> (raw)
In-Reply-To: <1fc79420f76d585231252e59d4fcf19b3e704ee3.1773432891.git.reinette.chatre@intel.com>
On Fri, 13 Mar 2026, Reinette Chatre wrote:
> As the CAT test reads the same buffer into different sized cache portions
> it compares the number of cache misses against an expected percentage
> based on the size of the cache portion.
>
> Systems and test conditions vary. The CAT test is a test of resctrl
> subsystem health and not a test of the hardware architecture so it is not
> required to place requirements on the size of the difference in cache
> misses, just that the number of cache misses when reading a buffer
> increase as the cache portion used for the buffer decreases.
>
> Remove additional constraint on how big the difference between cache
> misses should be as the cache portion size changes. Only test that the
> cache misses increase as the cache portion size decreases. This remains
> a good sanity check of resctrl subsystem health while reducing impact
> of hardware architectural differences and the various conditions under
> which the test may run.
>
> Increase the size difference between cache portions to additionally avoid
> any consequences resulting from smaller increments.
>
> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
> Tested-by: Chen Yu <yu.c.chen@intel.com>
> ---
> Changes since v2:
> - Add Chen Yu's tag.
> ---
> tools/testing/selftests/resctrl/cat_test.c | 33 ++++------------------
> 1 file changed, 5 insertions(+), 28 deletions(-)
>
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index f00b622c1460..8bc47f06679a 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -14,42 +14,20 @@
> #define RESULT_FILE_NAME "result_cat"
> #define NUM_OF_RUNS 5
>
> -/*
> - * Minimum difference in LLC misses between a test with n+1 bits CBM to the
> - * test with n bits is MIN_DIFF_PERCENT_PER_BIT * (n - 1). With e.g. 5 vs 4
> - * bits in the CBM mask, the minimum difference must be at least
> - * MIN_DIFF_PERCENT_PER_BIT * (4 - 1) = 3 percent.
> - *
> - * The relationship between number of used CBM bits and difference in LLC
> - * misses is not expected to be linear. With a small number of bits, the
> - * margin is smaller than with larger number of bits. For selftest purposes,
> - * however, linear approach is enough because ultimately only pass/fail
> - * decision has to be made and distinction between strong and stronger
> - * signal is irrelevant.
> - */
> -#define MIN_DIFF_PERCENT_PER_BIT 1UL
> -
> static int show_results_info(__u64 sum_llc_val, int no_of_bits,
> unsigned long cache_span,
> - unsigned long min_diff_percent,
> unsigned long num_of_runs, bool platform,
> __s64 *prev_avg_llc_val)
> {
> __u64 avg_llc_val = 0;
> - float avg_diff;
> int ret = 0;
>
> avg_llc_val = sum_llc_val / num_of_runs;
> if (*prev_avg_llc_val) {
> - float delta = (__s64)(avg_llc_val - *prev_avg_llc_val);
> -
> - avg_diff = delta / *prev_avg_llc_val;
> - ret = platform && (avg_diff * 100) < (float)min_diff_percent;
> -
> - ksft_print_msg("%s Check cache miss rate changed more than %.1f%%\n",
> - ret ? "Fail:" : "Pass:", (float)min_diff_percent);
> + ret = platform && (avg_llc_val < *prev_avg_llc_val);
>
> - ksft_print_msg("Percent diff=%.1f\n", avg_diff * 100);
> + ksft_print_msg("%s Check cache miss rate increased\n",
> + ret ? "Fail:" : "Pass:");
While I'm fine with removing the amount of change check, this no longer
shows any numbers which would be a bit annoying if/when there's a failure.
--
i.
> }
> *prev_avg_llc_val = avg_llc_val;
>
> @@ -58,10 +36,10 @@ static int show_results_info(__u64 sum_llc_val, int no_of_bits,
> return ret;
> }
>
> -/* Remove the highest bit from CBM */
> +/* Remove the highest bits from CBM */
> static unsigned long next_mask(unsigned long current_mask)
> {
> - return current_mask & (current_mask >> 1);
> + return current_mask & (current_mask >> 2);
> }
>
> static int check_results(struct resctrl_val_param *param, const char *cache_type,
> @@ -112,7 +90,6 @@ static int check_results(struct resctrl_val_param *param, const char *cache_type
>
> ret = show_results_info(sum_llc_perf_miss, bits,
> alloc_size / 64,
> - MIN_DIFF_PERCENT_PER_BIT * (bits - 1),
> runs, get_vendor() == ARCH_INTEL,
> &prev_avg_llc_val);
> if (ret)
>
next prev parent reply other threads:[~2026-03-27 17:45 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 20:32 [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 01/10] selftests/resctrl: Improve accuracy of cache occupancy test Reinette Chatre
2026-03-26 12:44 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 02/10] selftests/resctrl: Reduce interference from L2 occupancy during " Reinette Chatre
2026-03-26 12:56 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 03/10] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 04/10] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-03-26 13:03 ` Ilpo Järvinen
2026-03-26 14:34 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 05/10] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-03-27 17:28 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 06/10] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-03-27 17:30 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 07/10] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-03-27 17:34 ` Ilpo Järvinen
2026-03-27 23:19 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 08/10] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-03-27 17:45 ` Ilpo Järvinen [this message]
2026-03-27 23:21 ` Reinette Chatre
2026-03-31 8:07 ` Ilpo Järvinen
2026-03-31 17:39 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 09/10] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-03-27 17:47 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 10/10] selftests/resctrl: Reduce L2 impact on " Reinette Chatre
2026-03-27 17:49 ` Ilpo Järvinen
2026-03-27 23:22 ` Reinette Chatre
2026-03-31 19:13 ` [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Shuah Khan
2026-03-31 20:22 ` Reinette Chatre
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