From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 980AB1E32D4 for ; Tue, 3 Dec 2024 10:58:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223506; cv=none; b=Z/wd1Bj00JnCXetY5BYX0RwqFegTqOZgMv8yGbk5zCk/OjKyDVNQKEblLVAeYCTIPSL+Oa907fg02v25yGEo/S7YxVHw9q6FJPjkqUXG9IwA73x0KCXRNfAakN+VjYDdGlqzxm7LY+PqC/ltzxFVETZu32UR8OOhhlWGtG4hSh8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223506; c=relaxed/simple; bh=r5IzcIHpW1yeHzI+cxkcrwgUkSQv1jAL9yBPggXeYEM=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=sKDZysgvjHF6FssH4y2+iZBtSnAPHgZ/9KZJnpYrAg80uSiYbxJvoPiBIODiPp1Y5mmSIynHBmzXodttJZKF2J3Po5f+m1dSTXbCk1BeIJGlHFRfY75iFXt1rhN2qf7zhJlxPCBRwb0Ne79oSw867qkEeMcTq329XPKq2VoSuN8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RlAPaW5Z; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RlAPaW5Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733223504; x=1764759504; h=message-id:date:mime-version:subject:to:references:from: in-reply-to:content-transfer-encoding; bh=r5IzcIHpW1yeHzI+cxkcrwgUkSQv1jAL9yBPggXeYEM=; b=RlAPaW5ZBeFZM2GBHL/pwYe6X5/GprtMWPYHL45jfCW5gvGqh4SkoCRW Zr2Ff/o+vtkJmis6QDoaR4uBPFuarfbME5rbmfzU0RLRBO92NiT/TI+O3 zq+g4tzuxRmnmoqvcmTiU0zZYSdg4gQ6uubbiqkHUv4rIgYzVDuptD5vX nZ55YelsuKZZL8S3t8RscXf1tl3+eGJBQjsrmEDBW2BqtkzaSr3K3LSHS mqZ3ucZkCtI7sJdDwjcCgnIQY3qakxcRHIzyt6/hBcAgQ8Q179ER7sIza A+WvA2zYXIkovA+SuZCXOqjUBFv2Q0rOITsiQ2l1Xd0skQADJ6kbH6Hww w==; X-CSE-ConnectionGUID: wLTPe6MjRv+0eN5XJUm4rQ== X-CSE-MsgGUID: FmwGbvV6S4icjPkPRzc4hQ== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="43914257" X-IronPort-AV: E=Sophos;i="6.12,205,1728975600"; d="scan'208";a="43914257" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 02:58:24 -0800 X-CSE-ConnectionGUID: seQVHymXRPOzYEoDKLagXQ== X-CSE-MsgGUID: Tmu1TYCtSvCpZ6NYVzNtUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,205,1728975600"; d="scan'208";a="98400962" Received: from dhhellew-desk2.ger.corp.intel.com (HELO [10.245.245.10]) ([10.245.245.10]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 02:58:20 -0800 Message-ID: <4e67e781-df6d-45b8-be52-637ee5926bd7@linux.intel.com> Date: Tue, 3 Dec 2024 11:58:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] drm/i915: Add drm_panic support To: Jocelyn Falempe , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20241203092836.426422-1-jfalempe@redhat.com> <20241203092836.426422-6-jfalempe@redhat.com> Content-Language: en-US From: Maarten Lankhorst In-Reply-To: <20241203092836.426422-6-jfalempe@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hey, Den 2024-12-03 kl. 09:50, skrev Jocelyn Falempe: > This adds drm_panic support for a wide range of Intel GPU. I've > tested it only on 3 laptops, haswell (with 128MB of eDRAM), > cometlake and alderlake. > > * DPT: if I disable tiling on a framebuffer using DPT, then it > displays some other memory location. As DPT is enabled only for > tiled framebuffer, there might be some hardware limitations. This is because DPT points to the pagetable, when you disable tiling DPT is no longer used so the DPT is interpreted as a linear FB instead of a lookup table. The lookup table is necessarily smaller than the real FB, so you would need to overwrite part of the GGTT and point it to linear FB. I'm not sure what the fix is here as it would require a real GGTT mapping to fix, needing an allocation which might not succeed. Perhaps indicates a limitation to require a real pageflip to fbdev fb? Have you tested rotated by any chance? Cursor enabled? Overlay? I also think this may fail if there are flips queued. We should probably bite the bullet, reprogram the entire state into a known state, disable all overlay planes and cursor, reassign all watermarks for the primary and ensure any background work is killed where needed. Cheers, ~Maarten > * fbdev: On my haswell laptop, the fbdev framebuffer is configured > with tiling enabled, but really it's linear, because fbcon don't > know about tiling, and the panic screen is perfect when it's drawn > as linear. > Signed-off-by: Jocelyn Falempe > --- > .../gpu/drm/i915/display/intel_atomic_plane.c | 85 ++++++++++++++++++- > 1 file changed, 84 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c > index b7e462075ded3..58eb3b4c55fa5 100644 > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c > @@ -33,16 +33,20 @@ > > #include > #include > +#include > > #include > #include > +#include > #include > #include > #include > +#include > > #include "i915_config.h" > #include "i9xx_plane_regs.h" > #include "intel_atomic_plane.h" > +#include "intel_bo.h" > #include "intel_cdclk.h" > #include "intel_cursor.h" > #include "intel_display_rps.h" > @@ -50,6 +54,7 @@ > #include "intel_display_types.h" > #include "intel_fb.h" > #include "intel_fb_pin.h" > +#include "intel_fbdev.h" > #include "skl_scaler.h" > #include "skl_watermark.h" > > @@ -1198,14 +1203,92 @@ intel_cleanup_plane_fb(struct drm_plane *plane, > intel_plane_unpin_fb(old_plane_state); > } > > +/* Only used by drm_panic get_scanout_buffer() and panic_flush(), so it is > + * protected by the drm panic spinlock > + */ > +static struct iosys_map panic_map; > + > +static void intel_panic_flush(struct drm_plane *plane) > +{ > + struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); > + struct drm_i915_private *dev_priv = to_i915(plane->dev); > + struct drm_framebuffer *fb = plane_state->hw.fb; > + struct intel_plane *iplane = to_intel_plane(plane); > + > + /* Force a cache flush, otherwise the new pixels won't show up */ > + drm_clflush_virt_range(panic_map.vaddr, fb->height * fb->pitches[0]); > + > + /* Don't disable tiling if it's the fbdev framebuffer.*/ > + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev)) > + return; > + > + if (fb->modifier && iplane->disable_tiling) > + iplane->disable_tiling(iplane); > +} > + > +static int intel_get_scanout_buffer(struct drm_plane *plane, > + struct drm_scanout_buffer *sb) > +{ > + struct intel_plane_state *plane_state; > + struct drm_gem_object *obj; > + struct drm_framebuffer *fb; > + struct drm_i915_private *dev_priv = to_i915(plane->dev); > + void *ptr; > + > + if (!plane->state || !plane->state->fb || !plane->state->visible) > + return -ENODEV; > + > + plane_state = to_intel_plane_state(plane->state); > + fb = plane_state->hw.fb; > + obj = intel_fb_bo(fb); > + if (!obj) > + return -ENODEV; > + > + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev)) { > + ptr = intel_fbdev_get_vaddr(dev_priv->display.fbdev.fbdev); > + } else { > + /* can't disable tiling if DPT is in use */ > + if (intel_bo_is_tiled(obj) && HAS_DPT(dev_priv)) > + return -EOPNOTSUPP; > + > + ptr = intel_bo_panic_map(obj); > + } > + > + if (!ptr) > + return -ENOMEM; > + > + if (intel_bo_has_iomem(obj)) > + iosys_map_set_vaddr_iomem(&panic_map, ptr); > + else > + iosys_map_set_vaddr(&panic_map, ptr); > + > + sb->map[0] = panic_map; > + sb->width = fb->width; > + sb->height = fb->height; > + sb->format = fb->format; > + sb->pitch[0] = fb->pitches[0]; > + > + return 0; > +} > + > static const struct drm_plane_helper_funcs intel_plane_helper_funcs = { > .prepare_fb = intel_prepare_plane_fb, > .cleanup_fb = intel_cleanup_plane_fb, > }; > > +static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = { > + .prepare_fb = intel_prepare_plane_fb, > + .cleanup_fb = intel_cleanup_plane_fb, > + .get_scanout_buffer = intel_get_scanout_buffer, > + .panic_flush = intel_panic_flush, > +}; > + > void intel_plane_helper_add(struct intel_plane *plane) > { > - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > + if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) > + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); > + else > + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > } > > void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,