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[46.193.119.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ee019e44sm79184615e9.15.2026.04.14.04.59.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Apr 2026 04:59:25 -0700 (PDT) Message-ID: <4f009fa6-5fe1-4ba9-bacb-1bd8de820a98@gmail.com> Date: Tue, 14 Apr 2026 13:59:17 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata To: Marek Vasut , Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , Maxime Chevallier , Simon Horman , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Fidelio Lawson References: <20260414-ksz87xx_errata_low_loss_connections-v3-0-0e3838ca98c9@exotec.com> <20260414-ksz87xx_errata_low_loss_connections-v3-1-0e3838ca98c9@exotec.com> Content-Language: en-US From: Fidelio LAWSON In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 4/14/26 13:05, Marek Vasut wrote: > On 4/14/26 11:12 AM, Fidelio Lawson wrote: >> Implement the "Module 3: Equalizer fix for short cables" erratum from >> Microchip document DS80000687C for KSZ87xx switches. >> >> The issue affects short or low-loss cable links (e.g. CAT5e/CAT6), >> where the PHY receiver equalizer may amplify high-amplitude signals >> excessively, resulting in internal distortion and link establishment >> failures. >> >> KSZ87xx devices require a workaround for the Module 3 low-loss cable >> condition, controlled through the switch TABLE_LINK_MD_V indirect >> registers. >> >> The affected registers are part of the switch address space and are not >> directly accessible from the PHY driver. To keep the PHY-facing API >> clean and avoid leaking switch-specific details, model this errata >> control as vendor-specific Clause 22 PHY registers. >> >> A vendor-specific Clause 22 PHY register is introduced as a mode >> selector in PHY_REG_LOW_LOSS_CTRL, and ksz8_r_phy() / ksz8_w_phy() >> translate accesses to these bits into the appropriate indirect >> TABLE_LINK_MD_V accesses. >> >> The control register defines the following modes: >> 0: disabled (default behavior) >> 1: EQ training workaround >> 2: LPF 90 MHz >> 3: LPF 62 MHz >> 4: LPF 55 MHz >> 5: LPF 44 MHz > I may not fully understand this, but aren't the EQ and LPF settings > orthogonal ? You are right that EQ training and LPF bandwidth control are orthogonal from a hardware point of view. In this case, the interface is intentionally modeled after the erratum guidance rather than exposing all possible combinations. Microchip documents the workarounds as alternative solutions: "If work around 1 does not solve the short cable issue in a CAT-5E or CAT-6 application, change the work around 1 register (0x3C) to its default value (0x0A), and use the following settings" from: https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/Errata/KSZ87xx-Errata-DS80000687C.pdf If you’d prefer exposing these as orthogonal controls, I can revise the interface in the next iteration.