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Tue, 18 Mar 2025 06:57:00 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52I6ux0J002503 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Mar 2025 06:56:59 GMT Received: from [10.233.19.224] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 17 Mar 2025 23:56:55 -0700 Message-ID: <4fc69ebf-1bd4-428b-bae9-a4f67edee0f5@quicinc.com> Date: Tue, 18 Mar 2025 14:56:51 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support To: Manivannan Sadhasivam CC: , , , , , , , , , , , References: <20250226103600.1923047-1-quic_wenbyao@quicinc.com> <20250226103600.1923047-3-quic_wenbyao@quicinc.com> <20250314145035.h3nybvvko3ew37wl@thinkpad> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <20250314145035.h3nybvvko3ew37wl@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=67d9193c cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=GV8YIVLR6thIHoP4uU0A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: T0rQ1fDVlKvzzSXpiM4jgq6Pz45WpJVT X-Proofpoint-ORIG-GUID: T0rQ1fDVlKvzzSXpiM4jgq6Pz45WpJVT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_03,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180048 On 3/14/2025 10:50 PM, Manivannan Sadhasivam wrote: > On Wed, Feb 26, 2025 at 06:36:00PM +0800, Wenbin Yao wrote: >> From: Qiang Yu >> >> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >> whole PHY (hardware and register), no_csr reset only resets PHY hardware >> but retains register values, which means PHY setting can be skipped during >> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >> after that. >> >> Hence, determine whether the PHY has been enabled in bootloader by >> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >> available, skip BCR reset and PHY register setting to establish the PCIe >> link with bootloader - programmed PHY settings. >> >> Signed-off-by: Qiang Yu >> Signed-off-by: Wenbin Yao > Reviewed-by: Manivannan Sadhasivam > > One nit below. > >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++---- >> 1 file changed, 59 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> index 219266125cf2..c3642d1807e4 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> @@ -2805,6 +2805,7 @@ struct qmp_pcie { >> >> const struct qmp_phy_cfg *cfg; >> bool tcsr_4ln_config; >> + bool skip_init; >> >> void __iomem *serdes; >> void __iomem *pcs; >> @@ -3976,18 +3977,38 @@ static int qmp_pcie_init(struct phy *phy) >> { >> struct qmp_pcie *qmp = phy_get_drvdata(phy); >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> + void __iomem *pcs = qmp->pcs; >> + bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); >> int ret; >> >> + qmp->skip_init = qmp->nocsr_reset && phy_initialized; >> + /* >> + * We need to check the existence of init sequences in two cases: >> + * 1. The PHY doesn't support no_csr reset. >> + * 2. The PHY supports no_csr reset but isn't initialized by bootloader. >> + * As we can't skip init in these two cases. >> + */ >> + if (!qmp->skip_init && !cfg->tbls.serdes_num) { >> + dev_err(qmp->dev, "no init sequences are available\n"); > "Init sequence not available\n" > >> + return -EINVAL; > -ENODATA Will fix in the next version. > > - Mani > -- With best wishes Wenbin